CS 152 Computer Architecture and Engineering Lecture 5 Timing Op e e o rat Th r eF By tes our d e s o P e t 2005 9 13 s i e e g M c n John Lazzaro Sy www cs berkeley edu lazzaro rs TAs David Marquardt and Udam Saini www inst eecs berkeley edu cs152 CS 152 L5 Timing UC Regents Fall 2005 UCB Last Time Making a Test Plan Top down testing complete processor testing processor testing with self checks multi unit testing unit testing Bottom up testing CS 152 L5 Timing Which testing types are good for each epoch Epoch 1 unit testing early multi unit testing Epoch 2 Epoch 3 Epoch 4 processor testing with self checks processor testing with self checks complete processor testing multi unit testing multi unit testing unit testing unit testing verificati on processor testing with self checks later diagnostidiagnosti diagnosti cs Time cs cs processor assembly complete correctly executes single instructions correctly executes short programs UC Regents Fall 2005 UCB Last Time Works in ModelSim but Top down testing Idea get confidence in going to board earlier complete processor testing processor testing with self checks multi unit testing Epoch 1 Epoch 2 Epoch 3 Epoch 4 ModelSim ModelSim ModelSim ModelSim 80 80 80 20 Xilinx Xilinx Xilinx Xilinx 20 20 20 80 Time unit testing Bottom up testing processor assembly complete correctly executes single instructions correctly executes short programs Also catch Synplicity warnings and latch generated combinational loop errors earlier CS 152 L5 Timing UC Regents Fall 2005 UCB Today Determine minimum clock period Equal Combinational Logic Control Lines 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 wd RegDest 32 rd2 WE RegWr CS 152 L5 Timing ALUctr Equal Ext ExtOp MemToReg ALUsrc MemWr UC Regents Fall 2005 UCB Today s Lecture Timing Analysis Combinational logic delay Clocked logic and delay Xilinx and delay CS 152 L5 Timing UC Regents Fall 2005 UCB View from 10 000 Feet CS 152 L5 Timing UC Regents Fall 2005 UCB Architects draw blocks Circuit designers draw transistors Logic is where they meet CS 152 L5 Timing UC Regents Fall 2005 UCB Architects reach logic top down Rst Change Next State Combinational Logic next R wire R next G G next Y Y next R next Y next G assign next R rst 1 b1 change Y R assign next Y rst 1 b0 change G Y next G Using behavioral assign rst 1 b0 Verilog change and R G schematics CS 152 L5 Timing UC Regents Fall 2005 UCB EEs reach logic bottom up Small number of high performance logic circuits For some definition of small and high performance CS 152 L5 Timing Can you build a processor entirely out of NAND gates UC Regents Fall 2005 UCB Logic Synthesis often bridges the gap assign next R rst 1 b1 change Y R assign next Y rst 1 b0 change G Y assign next G in rstthe 1 b0 change R Still highest G performance designs human designers do some logic circuits and layout by hand CS 152 L5 Timing UC Regents Fall 2005 UCB A Logic Circuit Primer Models should be as simple as possible but no simpler Albert Einstein CS 152 L5 Timing UC Regents Fall 2005 UCB Inverters A simple transistor model pFET A switch On if gate is grounded 1 This model is too simple to be useful CS 152 L5 Timing 0 1 1 0 0 nFET A switch On if gate is at Vdd UC Regents Fall 2005 UCB Transistors as water valves If electrons are water molecules and a capacitor a bucket 1 A on p FET fills up the capacitor with charge 0 Water level Time 1 A on n FET empties the bucket 0 Water level CS 152 L5 Timing This model is often good Time UC Regents Fall 2005 UCB What is the bucket A gate s fan out Fan out The number of gate inputs driven by a gate s output Driving other gates slows a gate down Driving wires slows a gate down CS 152 L5 Timing UC Regents Fall 2005 UCB A closer look at fan out Driving more gates adds delay Linear model works for reasonable fan out CS 152 L5 Timing UC Regents Fall 2005 UCB Propagation delay graphs 1 0 CS 152 L5 Timing UC Regents Fall 2005 UCB Intuition Critical paths T2 might be the critical worstcase delay path T1 T2 x g a b c d e f If d going 0 to 1 switches x 0 to 1 delay is T1 If a going 0 to 1 switches x 0 to 1 delay is T2 Would you be surprised if T1 T2 Why CS 152 L5 Timing UC Regents Fall 2005 UCB Why might Wires have delay too Looks benign but CS 152 L5 Timing UC Regents Fall 2005 UCB Clocked Logic Circuits CS 152 L5 Timing UC Regents Fall 2005 UCB From Delay Models to Timing Analysis Timing Analysis What is the smallest T that produces correct operation CS 152 L5 Timing f T 1 MHz 1 s 10 MHz 100 ns 100 MHz 10 ns 1 GHz 1 ns UC Regents Fall 2005 UCB Timing Analysis and Logic Delay Register An Array of Flip Flops Combinational Logic CS 152 L5 Timing Can clock period T be smaller than worst case delay through CL UC Regents Fall 2005 UCB Flip Flops have internal delays D Q Value of D is sampled on positive clock edge sampled value for rest Q outputs of cycle t setup CLK D Q t clk to Q Where do Flip Flop delays come from Wait for VLSI lectures CS 152 L5 Timing UC Regents Fall 2005 UCB Flip Flop delays eat into time budget Combinational Logic ALU time budget CS 152 L5 Timing UC Regents Fall 2005 UCB Clock skew also eats into time budget CLKd CLKd As T 0 which circuit fails first CS 152 L5 Timing CLKd UC Regents Fall 2005 UCB Some Flip Flops have hold time t setup t inv t hold CLK D Q D D must stay stable here CLK Does flip flop hold time affect operation of this What is the intended circuit Under function of this what conditions circuit t clk to Q t inv t hold CS 152 L5 Timing UC Regents Fall 2005 UCB Searching for processor critical path Timing Analysis What is the smallest T that produces correct operation Must consider all connected register pairs Why might I suspect this one CS 152 L5 Timing UC Regents Fall 2005 UCB Searching for processor critical path Equal Combinational Logic Control Lines 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 wd RegDest 32 rd2 WE RegWr CS 152 L5 Timing ALUctr Equal Ext ExtOp MemToReg ALUsrc MemWr UC Regents Fall 2005 UCB Real Stuff Timing Estimation Closure Timing Estimation Predicting a processor s clock rate early in the project From The circuit and physical design of the POWER4 microprocessor IBM J Res and Dev 46 1 Jan 2002 J D Warnock et al CS 152 L5 Timing UC Regents Fall 2005 UCB Real …
View Full Document
Unlocking...