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Berkeley COMPSCI 152 - Lecture 5 – Timing

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Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53CS 152 L5: Timing UC Regents Fall 2005 © UCB2005-9-13John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 5 – Timingwww-inst.eecs.berkeley.edu/~cs152/TAs: David Marquardt and Udam Saini PosedgeOpeeratorSyncMeisters’The Four BytesUC Regents Fall 2005 © UCBCS 152 L5: TimingLast Time: Making a Test Plan ...Which testing types are good for each epoch?processorassemblycompletecorrectlyexecutes singleinstructionscorrectlyexecutes shortprogramsTimeEpoch 1 Epoch 2 Epoch 3 Epoch 4unit testingearlymultiunit testinglaterprocessortestingwithself-checksmulti-unit testingunit testingdiagnosticscomplete processor testingverificationprocessortestingwithself-checksdiagnosticsprocessortestingwithself-checksmulti-unit testingunit testingdiagnosticscomplete processor testingTop-downtestingBottom-uptestingunit testingmulti-unit testingprocessortestingwithself-checksUC Regents Fall 2005 © UCBCS 152 L5: TimingIdea: get confidence in “going to board” earlier ...processorassemblycompletecorrectlyexecutes singleinstructionscorrectlyexecutes shortprogramsTimeEpoch 1 Epoch 2 Epoch 3 Epoch 4complete processor testingTop-downtestingBottom-uptestingunit testingmulti-unit testingprocessortestingwithself-checksModelSim20 %Xilinx80 %ModelSim80 %Xilinx20 %ModelSim20 %Xilinx80 %ModelSim20 %Xilinx80 %Also: catch Synplicity “warnings and errors” earlier“latch generated”, “combinational loop detected”, etcLast Time: Works in ModelSim, but ...UC Regents Fall 2005 © UCBCS 152 L5: TimingToday: Determine minimum clock period32rd1RegFile32rd2WE32wd5rs15rs25wsExtRegDestALUsrcExtOpALUctrMemToRegMemWrEqualRegWrEqualControl LinesCombinational LogicUC Regents Fall 2005 © UCBCS 152 L5: TimingToday’s Lecture: Timing AnalysisXilinx and delayClocked logic and delayCombinational logic delayCS 152 L5: Timing UC Regents Fall 2005 © UCBView from 10,000 FeetUC Regents Fall 2005 © UCBCS 152 L5: TimingArchitects draw blocks ...Circuit designers draw transistors Logic is where they meet.UC Regents Fall 2005 © UCBCS 152 L5: TimingArchitects reach logic top-down ...Next State Combinational Logicnext_Gnext_R next_YR G YChangeRstwire next_R, next_Y, next_G;assign next_R = rst ? 1’b1 : (change ? Y : R); assign next_Y = rst ? 1’b0 : (change ? G : Y);assign next_G = rst ? 1’b0 : (change ? R : G); ... Using behavioral Verilog and schematics.UC Regents Fall 2005 © UCBCS 152 L5: TimingEEs reach logic bottom-up ...Can you build a processorentirely out of NAND gates?Small number of high-performance logic circuits. For some definition of “small” and “high-performance”UC Regents Fall 2005 © UCBCS 152 L5: TimingLogic Synthesis often bridges the gap ...assign next_R = rst ? 1’b1 : (change ? Y : R); assign next_Y = rst ? 1’b0 : (change ? G : Y);assign next_G = rst ? 1’b0 : (change ? R : G); Still, in the highest performance designs, human designers do (some) logic, circuits, and layout by hand.CS 152 L5: Timing UC Regents Fall 2005 © UCBA Logic Circuit Primer“Models should be as simple as possible, but no simpler ...” Albert Einstein.UC Regents Fall 2005 © UCBCS 152 L5: TimingInverters: A simple transistor model“1”“0”pFET.A switch. “On” if gate is grounded.nFET.A switch. “On” if gate is at Vdd.“1”“0”“1”“0”This model is too simple to be useful ...UC Regents Fall 2005 © UCBCS 152 L5: TimingTransistors as water valvesIf electrons are water molecules,and a capacitor a bucket ...A “on” p-FET fillsup the capacitor with charge. A “on” n-FET empties the bucket.“1”“0”TimeWater level“0”“1”TimeWater levelThis model is often good enough ...UC Regents Fall 2005 © UCBCS 152 L5: TimingWhat is the bucket? A gate’s “fan-out”.Driving other gates slows a gate down.Driving wires slows a gate down.“Fan-out”: The number of gate inputs driven by a gate’s output.UC Regents Fall 2005 © UCBCS 152 L5: TimingA closer look at fan-out ...Linear model works for reasonablefan-outDriving more gates adds delay.UC Regents Fall 2005 © UCBCS 152 L5: TimingPropagation delay graphs ...1->0UC Regents Fall 2005 © UCBCS 152 L5: TimingIntuition: Critical paths ...x = g(a, b, c, d, e, f)If d going 0-to-1 switches x 0-to-1, delay is T1.If a going 0-to-1 switches x 0-to-1, delay is T2.Would you be surprised if T1 > T2? Why?T1T2T2 might be the critical (worst-case delay) path.UC Regents Fall 2005 © UCBCS 152 L5: TimingWhy “might”? Wires have delay too ...Looksbenign,but ...CS 152 L5: Timing UC Regents Fall 2005 © UCBClocked Logic CircuitsUC Regents Fall 2005 © UCBCS 152 L5: TimingFrom Delay Models to Timing Analysisf T1 MHz 1 μs10 MHz 100 ns100 MHz 10 ns1 GHz 1 nsTiming AnalysisWhat is the smallest T that produces correct operation?UC Regents Fall 2005 © UCBCS 152 L5: TimingTiming Analysis and Logic DelayCan clock period T be smaller than worst-case delay through CL? Register:An Array of Flip-FlopsCombinational LogicUC Regents Fall 2005 © UCBCS 152 L5: TimingFlip Flops have internal delays ...D QCLKValue of D is sampled on positive clock edge.Q outputs sampled value for rest of cycle.DQt_setupt_clk-to-QWhere do Flip Flop delays come from? Wait for VLSI lectures.UC Regents Fall 2005 © UCBCS 152 L5: TimingFlip-Flop delays eat into “time budget”ALU “time budget”Combinational LogicUC Regents Fall 2005 © UCBCS 152 L5: TimingClock skew also eats into “time budget”As T →0, which circuit fails first?CLKdCLKdCLKdUC Regents Fall 2005 © UCBCS 152 L5: TimingSome Flip Flops have “hold” time ...Dt_setupCLKt_holdD must stay stable hereD QCLKDoes flip-flop hold time affect operation of this circuit? Under what conditions? t_clk-to-Q + t_inv > t_holdt_invWhat is the intended function of this circuit?UC Regents Fall 2005 © UCBCS 152 L5: TimingSearching for processor critical pathTiming AnalysisWhat is the smallest T that produces correct operation?Must considerall connectedregister pairs.?Why might I suspect this one?UC Regents Fall 2005 © UCBCS 152 L5:


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Berkeley COMPSCI 152 - Lecture 5 – Timing

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