CS152 Computer Architecture and Engineering Lecture 14 Introduction to Advanced Pipelining March 17 1999 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 3 17 99 UCB Spring 1999 CS152 Kubiatowicz Review Summary of Pipelining Basics Pipelines pass control information down the pipe just as data moves down pipe Forwarding Stalls handled by local control Hazards limit performance Structural need more HW resources Data need forwarding compiler scheduling Control early evaluation PC delayed branch prediction Increasing length of pipe increases impact of hazards pipelining helps instruction bandwidth not latency 3 17 99 UCB Spring 1999 CS152 Kubiatowicz Recap Pipeline Hazards I Fet ch DCD MemOpFetch OpFetch IFetch Structural Hazard I Fet ch DCD DCD OpFetch Jump IFetch IF DCD EX IF DCD EX IF 3 17 99 Control Hazard RAW read after write Data Hazard Mem WB DCD EX Mem WB IF DCD IF Store DCD Mem WB Exec DCD OF UCB Spring 1999 WAW Data Hazard write after write OF Ex RS Ex Mem WAR Data Hazard write read CS152after Kubiatowicz Recap Data Hazards Avoid some by design eliminate WAR by always fetching operands early DCD in pipe eleminate WAW by doing all WBs in order last stage static Detect and resolve remaining ones stall or forward if possible IF DCD EX IF DCD EX IF Mem WB DCD EX Mem WB IF DCD IF 3 17 99 RAW Data Hazard Mem WB DCD OF UCB Spring 1999 WAW Data Hazard OF Ex RS Ex Mem RAW Data Hazard CS152 Kubiatowicz IRmem D Separate control at each stage Reg File M Data Mem B Mem Access PC Next PC Equal Ex Ctrl Exec S WB Ctrl IRex A IRwb Dcd Ctrl Stalls Reg File IR Inst Mem Valid Mem Ctrl Recap Pipelined Processor for slides Bubbles Stalls propagate backwards to freeze previous stages Bubbles in pipeline introduced by placing Noops into local stage stall previous stages CS152 Kubiatowicz 3 17 99 UCB Spring 1999 Recap Data Stationary Control The Main Control generates the control signals during Reg Dec Control signals for Exec ExtOp ALUSrc are used 1 cycle later Control signals for Mem MemWr Branch are used 2 cycles later Control signals for Wr MemtoReg MemWr are used 3 cycles later Reg Dec ALUOp ALUOp RegDst MemWr Branch MemtoReg RegWr 3 17 99 RegDst MemWr Branch MemtoReg RegWr UCB Spring 1999 MemWr Branch MemtoReg RegWr Wr Mem Wr Register ExtOp ALUSrc Mem Ex Mem Register ExtOp ALUSrc ID Ex Register IF ID Register Main Control Exec MemtoReg RegWr CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topics Recap last lecture Review MIPS R3000 pipeline Administrivia Advanced Pipelining SuperScalar VLIW EPIC 3 17 99 UCB Spring 1999 CS152 Kubiatowicz Recap Record of Pending Writes IAU npc Current operand registers I mem Regs B op rw rs rt A im PC Pending writes hazard n op rw rs rwex rs rwmem regWme OR alu S n op rw m rs rwwb regWwb OR rt rwex regWex OR rt rwmem regWme OR D mem rt rwwb regWwb n op rw Regs 3 17 99 regWex OR UCB Spring 1999 CS152 Kubiatowicz Recap Resolve RAW by forwarding IAU npc I mem Regs op rw rs rt Forward mux B A im PC n op rw alu S n op rw Detect nearest valid write op operand register and forward into op latches bypassing remainder of the pipe Increase muxes to add paths from pipeline registers Data Forwarding Data Bypassing D mem m 3 17 99 Regs n op rw UCB Spring 1999 CS152 Kubiatowicz What about memory operations If instructions are initiated in order and operations always occur in the same stage there can be no hazards between memory operations op Rd Ra Rb What does delaying WB on arithmetic operations cost cycles op Rd Ra Rb hardware What about data dependence on loads R1 R4 R5 R2 Mem R2 I R3 R2 R1 Delayed Loads Can recognize this in decode stage and introduce bubble while stalling fetch stage hint for lab 5 Tricky situation R1 Mem R2 I Mem R3 34 R1 Handle with bypass in memory stage 3 17 99 UCB Spring 1999 Rd Rd A D B R Mem T to reg file CS152 Kubiatowicz Compiler Avoiding Load Stalls scheduled gcc spice 54 31 42 14 tex 0 unscheduled 65 25 20 40 60 80 loads stalling pipeline 3 17 99 UCB Spring 1999 CS152 Kubiatowicz What about Interrupts Traps Faults External Interrupts Allow pipeline to drain Load PC with interrupt address Faults within instruction restartable Force trap instruction into IF disable writes till trap hits WB must save multiple PCs or PC state Recall Precise Exceptions State of the machine is preserved as if program executed up to the offending instruction All previous instructions completed Offending instruction and all following instructions act as if they have not even started Same system code will work on different implementations 3 17 99 UCB Spring 1999 CS152 Kubiatowicz Exception Problem Exceptions Interrupts 5 instructions executing in 5 stage pipeline How to stop the pipeline Restart Who caused the interrupt Stage Problem interrupts occurring IF Page fault on instruction fetch misaligned memory access memory protection violation ID Undefined or illegal opcode EX Arithmetic exception MEM Page fault on data fetch misaligned memory access memory protection violation memory error Load with data page fault Add with instruction page fault Solution 1 interrupt vector instruction 2 interrupt ASAP restart everything incomplete 3 17 99 UCB Spring 1999 CS152 Kubiatowicz Another look at the exception problem Time Bad Inst Inst TLB fault Overflow IFetch Dcd Program Flow Data TLB Exec IFetch Dcd Mem WB Exec Mem WB Exec Mem WB Exec Mem IFetch Dcd IFetch Dcd WB Use pipeline to sort this out Pass exception status along with instruction Keep track of PCs for every instruction in pipeline Don t act on exception until it reache WB stage Handle interrupts through faulting noop in IF stage When instruction reaches WB stage Save PC EPC Interrupt vector addr PC Turn all instructions in earlier stages into noops 3 17 99 UCB Spring 1999 CS152 Kubiatowicz Exception Handling IAU npc I mem Regs B detect bad instruction address lw 2 20 5 A im n op rw PC Excp detect bad instruction Excp detect overflow alu S Excp detect bad data address D mem m 3 17 99 Regs Excp Allow exception to take effect UCB Spring 1999 CS152 Kubiatowicz Resolution Freeze above Bubble Below IAU npc I mem Regs op rw rs rt freeze PC bubble B A im n op rw alu S n op rw Flush accomplished by setting invalid bit in pipeline D mem m n op rw Regs 3 17 99 UCB Spring 1999 CS152 Kubiatowicz Administrivi a Policy on Homework Quizes Assuming that you have DONE homework and
View Full Document
Unlocking...