Recap Microprogramming CS152 Computer Architecture and Engineering Lecture 12 sequencer control datapath control Code ROM microinstruction Exceptions continued Introduction to Pipelining micro PC March 10 2003 CS152 Kubiatowicz Lec12 1 Recap Microprogramming To DataPath Microprogramming is a fundamental concept implement an instruction set by building a very simple processor and interpreting the instructions essential for very complex instructions and when few register transfers are possible overkill when ISA matches datapath 1 1 lecture slides http inst eecs berkeley edu cs152 UCB Spring 2003 For instance rt ALU rd ALU mem ALU Decode Decode Dispatch ROM Opcode John Kubiatowicz www cs berkeley edu kubitron 3 10 03 sequencer fetch dispatch sequential Decoders implement our P code language 3 10 03 CS152 Kubiatowicz Lec12 2 UCB Spring 2003 Recap Multicycle datapath book Microprogramming is a convenient method for implementing structured control state diagrams PCWr Random logic replaced by microPC sequencer and ROM 32 5 Rt 0 Rd busA A Rb Reg File Rw busW busB 1 2 Extend ExtOp 0 32 32 0 1 32 32 2 3 ALU Control 32 MemtoReg UCB Spring 2003 Zero 32 1 4 B 1 Mux 0 Imm 16 3 10 03 Ra 32 ALU Out CS152 Kubiatowicz Lec12 3 WrAdr 32 Din Dout 32 32 Rt Mux Ideal Memory 1 5 1 ALU 32 Mem Data Reg UCB Spring 2003 RAdr Mux 3 10 03 0 32 0 Rs Mux 32 1 Start with list of control signals 2 Group signals together that make sense vs random called fields 3 Place fields in some logical order e g ALU operation ALU operands first and microinstruction sequencing last 4 To minimize the width encode operations that will never be used at the same time 5 Create a symbolic legend for the microinstruction format showing name of field values and how they set the control signals ALUSelA RegWr Mux PC Design of a Microprogramming language RegDst 32 Instruction Reg Each line of ROM called a Pinstruction contains sequencer control values for control points limited state transitions branch to zero next sequential branch to Pinstruction address from displatch ROM PCSrc PCWrCond Zero IorD MemWr IRWr MemRd ALUOp ALUSelB CS152 Kubiatowicz Lec12 4 Field Name ALU SRC1 SRC2 dest ination Mem ory Memreg PCwrite Seq uencing 3 10 03 SRC Dest Mem Memreg 2 PCwrite 32 0 32 RAdr 32 Ideal Memory 1 WrAdr 32 Din Dout 32 0 Rs 32 Rt Rd Seq Values for Field Function of Field with Specific Value Add ALU adds Subt ALU subtracts Func ALU does function code Or ALU does logical OR PC 1st ALU input PC rs 1st ALU input Reg rs 4 2nd ALU input 4 Extend 2nd ALU input sign ext IR 15 0 Extend0 2nd ALU input zero ext IR 15 0 Extshft 2nd ALU input sign ex sl IR 15 0 rt 2nd ALU input Reg rt rd ALU Reg rd ALUout rt ALU Reg rt ALUout rt Mem Reg rt Mem Read PC Read memory using PC Read ALU Read memory using ALUout for addr Write ALU Write memory using ALUout for addr IR IR Mem PCwr PC PCSource PCSrc IF Zero then PCSource ALUout else ALU PCWrCond IF Zero then PC PCSource Seq Go to next sequential instruction CS152 Kubiatowicz UCB Spring Fetch Go to2003 the first microinstruction Lec12 7 Dispatch Dispatch using ROM 65 busA A Rb 5 Rt 0 Reg File Rw B 1 1 Mux 0 2 Extend 0 UCB Spring 2003 Zero 32 32 32 0 1 32 32 2 3 ALU Control 32 MemtoReg 32 1 4 busW busB ExtOp 3 10 03 Ra 5 1 ALU Out ALU SRC 1 PC Imm 16 Recap Group into Fields Order and Assign Names ALUSelA 32 32 CS152 Kubiatowicz Lec12 5 65 ALU UCB Spring 2003 PCSrc PCWrCond Destination Memory Zero MemWr IorD IRWr RegDst RegWr MemRd Mux 3 10 03 Effect ALU adds ALU subtracts ALU does function code ALU does logical OR 2nd ALU input 4 2nd ALU input Reg rt 2nd ALU input extended shift left 2 2nd ALU input extended PCWr Mux Signal name Value ALUOp 00 01 10 11 ALUSelB 00 01 10 11 PCWrite Mem Data Reg Effect when deasserted Effect when asserted 1st ALU operand PC 1st ALU operand Reg rs None Reg is written Reg write data input ALU Reg write data input memory Reg dest no rt Reg dest no rd None Memory at address is read MDR Mem addr MemWrite None Memory at address is written IorD Memory address PC Memory address S IRWrite None IR Memory PCWrite None PC PCSource PCWriteCond None IF ALUzero then PC PCSource PCSource PCSource ALU PCSource ALUout ExtOp Zero Extended Sign Extended Mux Signal name ALUSelA RegWrite MemtoReg RegDst MemRead Instruction Reg Multiple Bit Control Recap Group together related signals Mux Single Bit Control Recap Start with List of control signals ALUOp 8 ALUSelB CS152 Kubiatowicz Lec12 6 Recap Quick check what do these fieldnames mean Destination Code 00 01 10 11 Name rd ALU rt ALU rt MEM RegWrite 0 1 1 1 MemToReg X 0 0 1 Name 4 rt ExtShft Extend Extend0 ALUSelB X 00 01 10 11 11 ExtOp X X X 1 1 0 RegDest X 1 0 0 SRC2 Code 000 001 010 011 100 111 3 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec12 8 Recap Finite State Machine FSM Spec IR MEM PC Recap Microprogram it yourself Addr Fetch 0000 0001 instruction fetch PC PC 4 0000 ALUout PC SX decode 0001 ORi ALUout A fun B ALUout A or ZX 0100 0110 LW ALUout A SX 1000 M MEM ALUout 1001 BEQ SW ALUout A SX 1011 If A B then PC ALUout 0010 MEM ALUout B 1100 R rd ALUout 0101 3 10 03 R rt ALUout 0111 R rt M 1010 Memory Write back Execute R type CS152 Kubiatowicz Lec12 9 UCB Spring 2003 Recap Specific Sequencer from last lecture BEQ 0010 Rtype 0100 0101 ORI 0110 0111 LW 1000 1001 1010 SW 1011 1100 ALU SRC1 SRC2 Dest Memory Mem Reg PC Write Sequencing Add Add PC 4 PC Extshft Read PC Subt rs rt Func rs rt Or Add Seq Fetch rs Extend0 rt ALU Seq Fetch rs Extend rt MEM rs Extend 3 10 03 UCB Spring 2003 Seq Fetch Write ALU CS152 Kubiatowicz Lec12 10 UCB Spring 2003 user program Exception System Exception Handler return from exception 1 Address Select Logic Seq Seq Fetch Read ALU Add Fetch Exceptions Code Name Effect 00 fetch Next address 0 01 dispatch Next address dispatch ROM 10 seq Next address address 1 Adder Seq Dispatch ALUoutCond Called microPC or PC vs state register Opcode Dispatch state 000000 Rtype 0100 000100 BEQ 0010 001101 ORI 0110 100011 LW 1000 101011 SW 1011 ALU rd ALU 3 10 03 Sequencer based control unit from last lecture ROM IR normal control flow sequential jumps branches calls returns microPC Mux 2 1 0 0 ROM Opcode CS152 Kubiatowicz Lec12 11 Exception unprogrammed control transfer system takes action to handle the exception must record the address of the offending instruction record any other information necessary to return afterwards returns …
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