DOC PREVIEW
Berkeley COMPSCI 152 - Lecture 12 Exceptions Introduction to Pipelining

This preview shows page 1-2-3-4-5 out of 15 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 15 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 15 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 15 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 15 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 15 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 15 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.1CS152Computer Architecture and EngineeringLecture 12Exceptions (continued)Introduction to PipeliningMarch 10, 2003John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.2Recap: Microprogramming° Microprogramming is a fundamental concept• implement an instruction set by building a very simple processorand interpreting the instructions• essential for very complex instructions and when few register transfers are possible• overkill when ISA matches datapath 1-1sequencercontroldatapath controlmicro-PCµ-sequencer:fetch,dispatch,sequentialmicroinstruction (µ)DispatchROMOpcodeµ-Code ROMDecodeDecodeTo DataPathDecoders implement our P-code language:For instance:rt-ALUrd-ALUmem-ALU3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.3Recap: Microprogramming° Microprogramming is a convenient method for implementing structured control state diagrams:• Random logic replaced by microPC sequencer and ROM• Each line of ROM called a Pinstruction: contains sequencer control + values for control points• limited state transitions: branch to zero, next sequential,branch to Pinstruction address from displatch ROM° Design of a Microprogramming language1.Start with list of control signals2.Group signals together that make sense (vs. random): called “fields”3.Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last)4.To minimize the width, encode operations that will never be used at the same time5.Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.4Recap: Multicycle datapath (book)IdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControl32IRWrInstruction Reg32Reg FileRaRwbusWRb5532busA32busBRegWrRsRtMux01RtRdPCWrALUSelAMux01RegDstMux0132PCMemtoRegExtendExtOpMux01320123416Imm32<< 2ALUSelBMux1032ZeroZeroPCWrCondPCSrc32IorDMem Data RegALU OutBAMemRd3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.5Recap: Start with List of control signalsSignal name Effect when deasserted Effect when assertedALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs]RegWrite None Reg. is writtenMemtoReg Reg. write data input = ALU Reg. write data input = memoryRegDst Reg. dest. no. = rt Reg. dest. no. = rdMemRead None Memory at address is read, MDR <= Mem[addr]MemWrite None Memory at address is writtenIorD Memory address = PC Memory address = SIRWrite None IR <= MemoryPCWrite None PC <= PCSourcePCWriteCond None IF ALUzero then PC <= PCSourcePCSource PCSource = ALU PCSource = ALUoutExtOp Zero Extended Sign Extended Single Bit ControlSignal name Value EffectALUOp 00 ALU adds 01 ALU subtracts 10 ALU does function code11 ALU does logical ORALUSelB 00 2nd ALU input = 401 2nd ALU input = Reg[rt] 10 2nd ALU input = extended,shift left 2 11 2nd ALU input = extendedMultiple Bit Control3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.6Recap: Group together related signalsIdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControl32IRWrInstruction Reg32Reg FileRaRwbusWRb5532busA32busBRegWrRsRtMux01RtRdPCWrALUSelAMux01RegDstMux0132PCMemtoRegExtendExtOpMux01320123416Imm32<< 2ALUSelBMux1032ZeroZeroPCWrCondPCSrc32IorDMem Data RegALU OutBAMemRd$/865&65&DestinationMemoryPCWrite3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.7Recap: Group into Fields, Order and Assign NamesField Name Values for Field Function of Field with Specific ValueALU Add ALU addsSubt. ALU subtractsFunc ALU does function codeOr ALU does logical ORSRC1 PC 1st ALU input <= PCrs 1st ALU input <= Reg[rs]SRC2 4 2nd ALU input <= 4Extend 2nd ALU input <= sign ext. IR[15-0]Extend0 2nd ALU input <= zero ext. IR[15-0]Extshft 2nd ALU input <= sign ex., sl IR[15-0]rt 2nd ALU input <= Reg[rt]dest(ination) rd ALU Reg[rd] <= ALUout rt ALU Reg[rt] <= ALUoutrt Mem Reg[rt] <= Mem Mem(ory) Read PC Read memory using PCRead ALU Read memory using ALUout for addrWrite ALU Write memory using ALUout for addrMemreg IR IR <= MemPCwrite PCwr PC <= PCSourcePCSrcIF Zero then PCSource <= ALUout else ALUPCWrCond IF Zero then PC <= PCSource Seq(uencing) Seq Go to next sequential µinstructionFetch Go to the first microinstructionDispatchDispatch using ROM.SeqPCwriteMemregMemDestSRC2SRC1ALU3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.8Recap: Quick check: what do these fieldnames mean?Code Name RegWrite MemToReg RegDest00 --- 0 X X01 rd ALU 1 0 110 rt ALU 1 0 011 rt MEM 1 1 0Code Name ALUSelB ExtOp000 --- X X001 4 00 X010 rt 01 X011 ExtShft 10 1100 Extend 11 1111 Extend0 11 0Destination:SRC2:3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.9Recap: Finite State Machine (FSM) SpecIR <= MEM[PC]PC <= PC + 4R-typeALUout<= A fun BR[rd] <= ALUoutALUout<= A or ZXR[rt] <= ALUoutORiALUout<= A + SXR[rt] <= MM <= MEM[ALUout]LWALUout<= A + SXMEM[ALUout] <= BSW“instruction fetch”“decode”00000001010001010110011110001001101010111100BEQ0010If A = B then PC <= ALUoutALUout<= PC +SXExecuteMemoryWrite-back3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.10Recap: Microprogram it yourself!Addr ALU SRC1 SRC2 Dest. Memory Mem. Reg. PC Write SequencingFetch:0000: Add PC 4 Read PC IR ALU Seq0001: Add PC Extshft DispatchBEQ:0010: Subt. rs rt ALUoutCond. FetchRtype:0100: Func rs rt Seq0101: rd ALU FetchORI:0110: Or rs Extend0 Seq0111: rt ALU FetchLW:1000: Add rs Extend Seq1001: Read ALU Seq1010: rt MEM FetchSW:1011: Add rs Extend Seq1100: Write ALU Fetch3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.11Recap: Specific Sequencer from last lectureSequencer-based control unit from last lecture• Called “microPC” or “µPC” vs. state registerCode Name Effect00 fetch Next µaddress = 001 dispatch Next µaddress = dispatch ROM 10 seq Next µaddress = µaddress + 1ROM:OpcodemicroPC1µAddressSelectLogicAdderROMMux0012Opcode: Dispatch state000000: Rtype (0100)000100: BEQ (0010)001101: ORI (0110)100011: LW (1000)101011: SW (1011)3/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec12.12Exceptions° Exception = unprogrammed control transfer• system takes action to handle the exception- must record the address of the offending instruction- record any other information necessary to return afterwards• returns control to user• must save & restore user state° Allows


View Full Document

Berkeley COMPSCI 152 - Lecture 12 Exceptions Introduction to Pipelining

Documents in this Course
Quiz 5

Quiz 5

9 pages

Memory

Memory

29 pages

Quiz 5

Quiz 5

15 pages

Memory

Memory

29 pages

Memory

Memory

35 pages

Memory

Memory

15 pages

Quiz

Quiz

6 pages

Midterm 1

Midterm 1

20 pages

Quiz

Quiz

12 pages

Memory

Memory

33 pages

Quiz

Quiz

6 pages

Homework

Homework

19 pages

Quiz

Quiz

5 pages

Memory

Memory

15 pages

Load more
Download Lecture 12 Exceptions Introduction to Pipelining
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lecture 12 Exceptions Introduction to Pipelining and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 12 Exceptions Introduction to Pipelining 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?