CS 152 Final Project A Green Bovine Superscalar Processor by MooCrew Part Deux Jonathan Choy Yolanda Hong Arlene Gabriana Lijue Zhong Nguyen Tran Presentation Outline Project Features Superscalar Performance Branch Prediction Multiply Divide Testing Lessons Learned Superscalar Big Picture DECODE even EX MEM FETCH DECODE odd EX WB D1 F D2 Dual Issue of Instructions We fetch two instructions at a time from the Instruction Cache Issue unit determines whether two instructions are allowed to go together If two instructions cannot be executed simultaneously we store the second one for later IF ID TIME 1 2 3 1X2 4 Rollback 4 5 2 3 4 X EX M EX W Memory and WB Add second ALU for multiple EX operations Cache controller can do any two memory operations at the same time Put twice as many read write ports for Register file Instruction and Data Caches Added forwarding and hazard control addr1 din1 addr2 din2 Data Cache dout1 dout2 Register File Cycle Time and Critical Path The smallest stepsize we can use for our processor is 17 ns 34ns cycle time Our critical path is shown below Branch Prediction Branch Controller branch Predict Taken Predict Not Taken Taken1 Taken2 Not1 Not2 Predict Taken Predict Not Taken branch Should we take the branch Next PC Logic Can we Branch Target Buffer PC from IF Stage Branch Target Address POOF PC To Fetch Superscalar Branch Prediction Branch Instruction can be either an Even or Odd instruction as fetched by the IF stage but we only send branches in the even pipeline delay slot goes into odd Even instruction predict in IF stage based on BTB and FSM Odd instruction propagate the BTB value and prediction along with the instruction to ID stage do the prediction there Recovering from Misprediction Always predict branch in IF stage and compute the branch condition in the ID stage we feed those signals back to the branch controller in the IF stage to flush the bad instruction and restore the correct PC if mispredicted Odd Branch on Mispredict Even Branch on Mispredict IF ID IF ID Br Br Pred P 4 Oops Fix F 4 Br Bubble B 4 B 8 Br Pred P 4 Oops Br B 4 Fix F 4 Bubble Multiply Divide Unit Signed Operations Make negative operands positive Feed them into unsigned mult div unit When it s done negate results if needed Send done signal to the datapath Unsigned Operation Multiply Algorithm 3 Divide Algorithm 3 non restoring version neg neg unsigned mult div unit neg neg multiplicand divisor ALU Control multiplier rem prod quotient Testing Methodology Fix monitor to see what is going on in both odd and even pipelines Test individual components separately before we put them together Test branch prediction and multiply divide unit independently with our single issue datapath Put everything together and run our own battery of tests Run the mystery programs from previous labs Lessons Learned Keep it simple stupid Testing methodology Design Extra Credit really means optional Moo Conclusions
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