CS 152 Computer Architecture and Engineering Lecture 14 Advanced Superscalars Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 March 11 2010 CS152 Spring 2010 Last time in Lecture 13 Register renaming removes WAR WAW hazards Instruction execution divided into four major stages Instruction Fetch Decode Rename Execute Complete Commit Control hazards are serious impediment to superscalar performance Dynamic branch predictors can be quite accurate 95 and avoid most control hazards Branch History Tables BHTs just predict direction later in pipeline Just need a few bits per entry 2 bits gives hysteresis Need to decode instruction bits to determine whether this is a branch and what the target address is March 11 2010 CS152 Spring 2010 2 Limitations of BHTs Only predicts branch direction Therefore cannot redirect fetch stream until after branch target is determined Correctly predicted taken branch penalty Jump Register penalty A PC Generation Mux P Instruction Fetch Stage 1 F Instruction Fetch Stage 2 B Branch Address Calc Begin Decode I Complete Decode J Steer Instructions to Functional units R Register File Read E Integer Execute Remainder of execute pipeline another 6 stages UltraSPARC III fetch pipeline March 11 2010 CS152 Spring 2010 3 Branch Target Buffer predicted target BPb Branch Target Buffer 2k entries IMEM k PC target BP BP bits are stored with the predicted target address IF stage If BP taken then nPC target else nPC PC 4 later check prediction if wrong then kill the instruction and update BTB BPb else update BPb March 11 2010 CS152 Spring 2010 4 Address Collisions 132 Jump 100 Assume a 128 entry BTB 1028 Add target 236 BPb take Instruction What will be fetched after the instruction at 1028 Memory BTB prediction Correct target 236 1032 kill PC 236 and fetch PC 1032 Is this a common occurrence Can we avoid these bubbles March 11 2010 CS152 Spring 2010 5 BTB is only for Control Instructions BTB contains useful information for branch and jump instructions only Do not update it for other instructions For all other instructions the next PC is PC 4 How to achieve this effect without decoding the instruction March 11 2010 CS152 Spring 2010 6 Branch Target Buffer BTB I Cache 2k entry direct mapped BTB PC can also be associative Entry PC Valid predicted target PC valid target k match Keep both the branch PC and target PC in the BTB PC 4 is fetched if match fails Only taken branches and jumps held in BTB Next PC determined before branch fetched and decoded March 11 2010 CS152 Spring 2010 7 Combining BTB and BHT BTB entries are considerably more expensive than BHT but can redirect fetches at earlier stage in pipeline and can accelerate indirect branches JR BHT can hold many more entries and is more accurate BHT in later pipeline stage corrects when BTB misses a predicted taken branch A PC Generation Mux BTB P Instruction Fetch Stage 1 F Instruction Fetch Stage 2 BHT B Branch Address Calc Begin Decode I Complete Decode J Steer Instructions to Functional units R Register File Read E Integer Execute BTB BHT only updated after branch resolves in E stage March 11 2010 CS152 Spring 2010 8 Uses of Jump Register JR Switch statements jump to address of matching case BTB works well if same case used repeatedly Dynamic function call jump to run time function address BTB works well if same function usually called e g in C programming when objects have same type in virtual function call Subroutine returns jump to return address BTB works well if usually return to the same place Often one function called from many distinct call sites How well does BTB work for each of these cases March 11 2010 CS152 Spring 2010 9 Subroutine Return Stack Small structure to accelerate JR for subroutine returns typically much more accurate than BTBs fa fb fb fc fc fd Pop return address when subroutine return decoded Push call address when function call executed fd fc fb March 11 2010 CS152 Spring 2010 k entries typically k 8 16 10 Mispredict Recovery In order execution machines Assume no instruction issued after branch can write back before branch resolves Kill all instructions in pipeline behind mispredicted branch Out of order execution Multiple instructions following branch in program order can complete before branch resolves March 11 2010 CS152 Spring 2010 11 In Order Commit for Precise Exceptions In order Fetch Out of order Reorder Buffer Decode Commit Kill Kill Kill In order Execute Inject handler PC Exception Instructions fetched and decoded into instruction reorder buffer in order Execution is out of order out of order completion Commit write back to architectural state i e regfile memory is in order Temporary storage needed in ROB to hold results before commit March 11 2010 CS152 Spring 2010 12 Branch Misprediction in Pipeline Inject correct PC Branch Prediction Kill Kill PC Fetch Decode Branch Resolution Kill Reorder Buffer Commit Complete Execute Can have multiple unresolved branches in ROB Can resolve branches out of order by killing all the instructions in ROB that follow a mispredicted branch March 11 2010 CS152 Spring 2010 13 Recovering ROB Renaming Table t vv t t t vv Rename Table r1 Rename Snapshots Registe r File r2 Ptr2 next to commit Ins use exec op p1 src1 p2 src2 pd dest data t1 t2 tn rollback next available Ptr1 next available Reorder buffer Load Unit FU FU FU Store Unit Commit t result Take snapshot of register rename table at each predicted branch recover earlier snapshot if branch mispredicted March 11 2010 CS152 Spring 2010 14 Speculating Both Directions An alternative to branch prediction is to execute both directions of a branch speculatively resource requirement is proportional to the number of concurrent speculative executions only half the resources engage in useful work when both directions of a branch are executed speculatively branch prediction takes less resources than speculative execution of both paths With accurate branch prediction it is more cost effective to dedicate all resources to the predicted direction March 11 2010 CS152 Spring 2010 15 Data in ROB Design HP PA8000 Pentium Pro Core2Duo Register File holds only committed state Ins use exec op p1 src1 p2 src2 pd dest data t1 t2 tn Reorder buffer Load Unit FU FU FU Store Unit Commit t result On dispatch into ROB ready sources can be in regfile or in ROB dest copied into src1 src2 if ready before dispatch On
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