CS 152 Computer Architecture and Engineering Lecture 1 - IntroductionComputing Devices Then…Computing Devices NowWhat is Computer Architecture?Abstraction Layers in Modern SystemsUniprocessor PerformanceThe End of the Uniprocessor EraConventional Wisdom in Computer ArchitectureSea Change in Chip DesignDéjà vu all over again?Problems with Sea ChangeSlide 12The New CS152CS 152 Course FocusThe New CS152 Executive SummaryCS152 AdministriviaCS152 Structure and SyllabusCS152 Course ComponentsCS152 LabsRelated CoursesComputer Architecture: A Little HistoryCharles Babbage 1791-1871 Lucasian Professor of Mathematics, Cambridge University, 1827-1839Charles BabbageDifference Engine A machine to compute mathematical tablesDifference EngineAnalytic EngineAnalytic Engine The first conception of a general-purpose computerThe first programmer Ada Byron aka “Lady Lovelace” 1815-52Babbage’s InfluenceHarvard Mark ILinear Equation Solver John Atanasoff, Iowa State UniversityElectronic Numerical Integrator and Computer (ENIAC)Electronic Discrete Variable Automatic Computer (EDVAC)Stored Program ComputerTechnology IssuesDominant Problem: ReliabilityCommercial Activity: 1948-52And then there was IBM 701Computers in mid 50’sThe IBM 650 (1953-4)Programmer’s view of the IBM 650The Earliest Instruction SetsProgramming: Single Accumulator MachineSelf-Modifying CodeIndex Registers Tom Kilburn, Manchester University, mid 50’sUsing Index RegistersOperations on Index RegistersEvolution of Addressing ModesVariety of Instruction FormatsMore Instruction FormatsData Formats and Memory AddressesSoftware DevelopmentsCompatibility Problem at IBMIBM 360 : Design Premises Amdahl, Blaauw and Brooks, 1964IBM 360: A General-Purpose Register (GPR) MachineIBM 360: Initial ImplementationsIBM 360: Forty years later… The zSeries z990 MicroprocessorAnd in conclusion …AcknowledgementsCS 152 Computer Architecture and Engineering Lecture 1 - Introduction Krste AsanovicElectrical Engineering and Computer SciencesUniversity of California at Berkeleyhttp://www.eecs.berkeley.edu/~krstehttp://inst.eecs.berkeley.edu/~cs1521/22/2008 CS152-Spring’082Computing Devices Then…EDSAC, University of Cambridge, UK, 19491/22/2008 CS152-Spring’083Computing Devices NowQuickTime™ and aTIFF (Uncompressed) decompressorare needed to see this picture.QuickTime™ and aTIFF (Uncompressed) decompressorare needed to see this picture.QuickTime™ and aTIFF (Uncompressed) decompressorare needed to see this picture.QuickTime™ and aTIFF (Uncompressed) decompressorare needed to see this picture.RobotsSupercomputersAutomobilesLaptopsSet-top boxesGamesSmart phonesServersMedia PlayersSensor NetsRoutersCameras1/22/2008 CS152-Spring’084What is Computer Architecture?ApplicationPhysicsGap too large to bridge in one step(but there are exceptions, e.g. magnetic compass)In its broadest definition, computer architecture is the design of the abstraction layers that allow us to implement information processing applications efficiently using available manufacturing technologies.1/22/2008 CS152-Spring’085Abstraction Layers in Modern SystemsAlgorithmGates/Register-Transfer Level (RTL)ApplicationInstruction Set Architecture (ISA)Operating System/Virtual MachinesMicroarchitectureDevicesProgramming LanguageCircuitsPhysicsOriginal domain of the computer architect(‘50s-’80s)Domain of recent computer architecture(‘90s)1/22/2008 CS152-Spring’0861101001000100001978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006Performance (vs. VAX-11/780) 25%/year52%/year??%/yearUniprocessor Performance• VAX : 25%/year 1978 to 1986• RISC + x86: 52%/year 1986 to 2002• RISC + x86: ??%/year 2002 to presentFrom Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 4th edition, October, 2006What happened????1/22/2008 CS152-Spring’087The End of the Uniprocessor EraSingle biggest change in the history of computing systems1/22/2008 CS152-Spring’088•Old Conventional Wisdom: Power is free, Transistors expensive•New Conventional Wisdom: “Power wall” Power expensive, Transistors free (Can put more on chip than can afford to turn on)•Old CW: Sufficient increasing Instruction-Level Parallelism via compilers, innovation (pipelining, superscalar, out-of-order, speculation, VLIW, …)•New CW: “ILP wall” law of diminishing returns on more HW for ILP •Old CW: Multiplies are slow, Memory access is fast•New CW: “Memory wall” Memory slow, multiplies fast (200 clock cycles to DRAM memory, 4 clocks for multiply)•Old CW: Uniprocessor performance 2X / 1.5 yrs•New CW: Power Wall + ILP Wall + Memory Wall = Brick Wall–Uniprocessor performance now 2X / 5(?) yrs Sea change in chip design: multiple “cores” (2X processors per chip / ~ 2 years)»More, simpler processors are more power efficientConventional Wisdom in Computer Architecture1/22/2008 CS152-Spring’089Sea Change in Chip Design•Intel 4004 (1971): 4-bit processor,2312 transistors, 0.4 MHz, 10 micron PMOS, 11 mm2 chip • Processor is the new transistor? •RISC II (1983): 32-bit, 5 stage pipeline, 40,760 transistors, 3 MHz, 3 micron NMOS, 60 mm2 chip•125 mm2 chip, 0.065 micron CMOS = 2312 RISC II+FPU+Icache+Dcache–RISC II shrinks to ~ 0.02 mm2 at 65 nm–Caches via DRAM or 1 transistor SRAM?1/22/2008 CS152-Spring’0810Déjà vu all over again?•Multiprocessors imminent in 1970s, ‘80s, ‘90s, …•“… today’s processors … are nearing an impasse as technologies approach the speed of light..”David Mitchell, The Transputer: The Time Is Now (1989)•Transputer was premature Custom multiprocessors tried to beat uniprocessors Procrastination rewarded: 2X seq. perf. / 1.5 years• “We are dedicating all of our future product development to multicore designs. … This is a sea change in computing”Paul Otellini, President, Intel (2004) •Difference is all microprocessor companies have switched to multiprocessors (AMD, Intel, IBM, Sun; all new Apples 2+ CPUs) Procrastination penalized: 2X sequential perf. / 5 yrs Biggest programming challenge: from 1 to 2 CPUs1/22/2008 CS152-Spring’0811Problems with Sea Change •Algorithms, Programming Languages, Compilers, Operating Systems, Architectures, Libraries, … not ready to supply Thread-Level Parallelism or Data-Level Parallelism for 1000 CPUs / chip, •Architectures not ready for 1000 CPUs / chip–Unlike Instruction-Level Parallelism, cannot be
View Full Document
Unlocking...