CS 152 Computer Architecture and Engineering Lecture 14 Advanced Superscalars Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 Last time in Lecture 13 Register renaming removes WAR WAW hazards Instruction execution divided into four major stages Instruction Fetch Decode Rename Execute Complete Commit Control hazards are serious impediment to superscalar performance Dynamic branch predictors can be quite accurate 95 and avoid most control hazards Branch History Tables BHTs just predict direction later in pipeline Just need a few bits per entry 2 bits gives hysteresis Need to decode instruction bits to determine whether this is a branch and what the target address is 3 17 2009 CS152 Spring 09 2 Dynamic Branch Prediction learning based on past behavior Temporal correlation The way a branch resolves may be a good predictor of the way it will resolve at the next execution Spatial correlation Several branches may resolve in a highly correlated manner a preferred path of execution 3 17 2009 3 CS152 Spring 09 Branch Prediction Bits Assume 2 BP bits per instruction Change the prediction after two consecutive mistakes taken taken take right taken take wrong taken taken take right taken taken take wrong taken BP state predict take take x last prediction right wrong 3 17 2009 CS152 Spring 09 4 Branch History Table Fetch PC 00 k I Cache BHT Index 2k entry BHT 2 bits entry Instruction Opcode offset Branch Target PC Taken Taken 4K entry BHT 2 bits entry 80 90 correct predictions 3 17 2009 CS152 Spring 09 5 Exploiting Spatial Correlation Yeh and Patt 1992 if x i y if x i c 7 then 1 5 then 4 If first condition false second condition also false History register H records the direction of the last N branches executed by the processor 3 17 2009 CS152 Spring 09 6 Two Level Branch Predictor Pentium Pro uses the result from the last two branches to select one of the four sets of BHT bits 95 correct 00 Fetch PC k 2 bit global branch history shift register Shift in Taken Taken results of each branch Taken Taken 3 17 2009 CS152 Spring 09 7 Limitations of BHTs Only predicts branch direction Therefore cannot redirect fetch stream until after branch target is determined Correctly predicted taken branch penalty Jump Register penalty A PC Generation Mux P Instruction Fetch Stage 1 F Instruction Fetch Stage 2 B Branch Address Calc Begin Decode I Complete Decode J Steer Instructions to Functional units R Register File Read E Integer Execute Remainder of execute pipeline another 6 stages UltraSPARC III fetch pipeline 3 17 2009 CS152 Spring 09 8 Branch Target Buffer predicted target BPb Branch Target Buffer 2k entries IMEM k PC target BP BP bits are stored with the predicted target address IF stage If BP taken then nPC target else nPC PC 4 later check prediction if wrong then kill the instruction and update BTB BPb else update BPb 3 17 2009 9 CS152 Spring 09 Address Collisions 132 Jump 100 Assume a 128 entry BTB 1028 Add target 236 BPb take Instruction What will be fetched after the instruction at 1028 Memory BTB prediction Correct target Is this a common occurrence Can we avoid these bubbles 3 17 2009 CS152 Spring 09 10 BTB is only for Control Instructions BTB contains useful information for branch and jump instructions only Do not update it for other instructions For all other instructions the next PC is PC 4 How to achieve this effect without decoding the instruction 3 17 2009 11 CS152 Spring 09 Branch Target Buffer BTB I Cache 2k entry direct mapped BTB PC can also be associative Entry PC Valid predicted target PC valid target k match Keep both the branch PC and target PC in the BTB PC 4 is fetched if match fails Only taken branches and jumps held in BTB Next PC determined before branch fetched and decoded 3 17 2009 CS152 Spring 09 12 Consulting BTB Before Decoding 132 Jump 100 entry PC 132 target 236 BPb take 1028 Add The match for PC 1028 fails and 1028 4 is fetched eliminates false predictions after ALU instructions BTB contains entries only for control transfer instructions more room to store branch targets 3 17 2009 CS152 Spring 09 13 Combining BTB and BHT BTB entries are considerably more expensive than BHT but can redirect fetches at earlier stage in pipeline and can accelerate indirect branches JR BHT can hold many more entries and is more accurate BTB BHT in later pipeline stage corrects when BTB misses a predicted taken branch BHT A PC Generation Mux P Instruction Fetch Stage 1 F Instruction Fetch Stage 2 B Branch Address Calc Begin Decode I Complete Decode J Steer Instructions to Functional units R Register File Read E Integer Execute BTB BHT only updated after branch resolves in E stage 3 17 2009 CS152 Spring 09 14 Uses of Jump Register JR Switch statements jump to address of matching case Dynamic function call jump to run time function address Subroutine returns jump to return address How well does BTB work for each of these cases 3 17 2009 15 CS152 Spring 09 Subroutine Return Stack Small structure to accelerate JR for subroutine returns typically much more accurate than BTBs fa fb fb fc fc fd Pop return address when subroutine return decoded Push call address when function call executed fd fc k entries typically k 8 16 fb 3 17 2009 CS152 Spring 09 16 Mispredict Recovery In order execution machines Assume no instruction issued after branch can write back before branch resolves Kill all instructions in pipeline behind mispredicted branch Out of order execution Multiple instructions following branch in program order can complete before branch resolves 3 17 2009 17 CS152 Spring 09 In Order Commit for Precise Exceptions In order Fetch Out of order Reorder Buffer Decode Kill In order Commit Kill Kill Execute Inject handler PC Exception Instructions fetched and decoded into instruction reorder buffer in order Execution is out of order out of order completion Commit write back to architectural state i e regfile memory is in order Temporary storage needed in ROB to hold results before commit 3 17 2009 CS152 Spring 09 18 Branch Misprediction in Pipeline Inject correct PC Branch Prediction Branch Resolution Kill Kill Kill PC Fetch Commit Reorder Buffer Decode Complete Execute Can have multiple unresolved branches in ROB Can resolve branches out of order by killing all the instructions in ROB that follow a mispredicted branch 3 17 2009 19 CS152 Spring 09 Recovering ROB Renaming Table Rename
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