From ASIC to ASIP: The Next Design DiscontinuityKurt Keutzer Dept. of EECS, UC Berkeley Berkeley, CA, USA Email: [email protected] Sharad Malik Dept. of EE, Princeton University Princeton, NJ, USA Email: [email protected] A. Richard Newton Dept. of EECS, UC Berkeley Berkeley, CA, USA Email: [email protected] Abstract A variety of factors is making it increasingly difficult and ex-pensive to design and manufacture traditional Application Spe-cific Integrated Circuits (ASICs). This has started a significant move towards the use of programmable solutions of various forms – increasingly referred to as programmable platforms. For the platform manufacturer, programmability provides higher volume to amortize design and manufacturing costs, as the same platform can be used over multiple related applications, as well as over generations of an application. For the application implementer, programmability provides a lower risk and shorter time-to-market implementation path. The flexibility provided by programmability comes with a performance and power overhead. This can be sig-nificantly mitigated by using application specific platforms, also referred to as Application Specific Instruction Set Processors (ASIPs). This paper details the reasons for this significant change in application implementation philosophy, provides illustrative contemporary evidence of this change, examines the space of application specific platforms, outlines fundamental problems in their development, and finally presents a methodology to deal with this changing design style. Keywords Application Specific Integrated Circuits, Application Specific Instruction Set Processors, ASIC, ASIP, Programmable platforms, Design methodology. 1. INTRODUCTION Designing an ASIC in today’s deep submicron geometries is harder than ever, and the problems continue to worsen with shrinking geometries. Design tools are finding it difficult to han-dle the complexity and electrical design challenges posed by each new technology generation. The net consequence is increasingly lowered design productivity despite increasingly expensive design tools. ASIC manufacturing costs are also rising – multi-million dollar mask sets are projected for sub-100nm designs. These high non-recurring design and manufacturing costs imply either larger break even volumes at fixed per-unit costs, or prohibitive per-unit costs at fixed volumes. An alternative implementation style to ASICs that is rapidly emerging is the use of programmable solutions - alternatively referred to as programmable platforms, or Application Specific Instruction Set Processors (ASIPs). For the hardware developer the programmability of these devices enables a larger volume, as multiple related applications, as well as different generations of an application can be mapped onto the same ASIP. For the appli-cation developer, a programmable solution provides a much lower risk as well as a predictable and shorter time-to-market solution – writing and debugging software is cheaper than designing, debug-ging and manufacturing working hardware. In fact, there are signs of a revolution afoot, with an increasing trend of engineers from hardware application groups going off and rapidly deploying the application in software on available domain specialized proces-sors [1]. Historically, designers adopting manageable alternatives have heralded a significant change in design methodology – much be-fore the change in design methodology has stabilized and accept-able tool flows are widely available. The move from schematic capture to logic synthesis and simulation in the mid-80s was led by designers unwilling to deal with increasing complexity in a non-scalable methodology. Home-grown rudimentary simulation and synthesis tools were enough to deliver enough increased pro-ductivity to these engineers for them to abandon the old tools and also some design optimality. It did not take mature stable tools for them to make the change – those tools followed to convert the trend to accepted design practice on a larger scale. We believe that we are at a similar watershed in design imple-mentation practice today. The individual ASIC designers that are today abandoning hardware design for the productivity benefit of software solutions on an ASIP, even at some loss of design qual-ity (measured in area, delay, power), portend the acceptable de-sign practice of tomorrow. This paper focuses on the tools and methodologies that will get us rapidly to that tomorrow by focus-ing on the development of these ASIPs. This paper is organized as follows. We start by motivating the move from ASICs to ASIPs due to increasing design and manu-facturing costs in Section 2. In Section 3 we describe the various axes along which we can characterize ASIPs. Section 4 points to significant contemporary evidence of the rise of ASIPs. The prob-lems in existing methodologies for ASIP development is the focus of Section 5. In Section 6 we address these methodology gaps by outlining a disciplined methodology for ASIP development. Fi-nally we summarize in Section 7. 2. MOTIVATION Increasing Design Costs Designing an integrated circuit is getting increasingly expen-sive with each succeeding generation. Design difficulties arise from four distinct causes: Deep-Submicron Effects (DSM): Designing in deep sub-micron geometries (generally accepted as < 250nm) raises a host of new electrical design challenges. The primary change is the increase in interconnect delay as a fraction of the gate delay due to scaling effects. Since this is not avail-able till physical design (place and route) is over, the tradi-tional synthesis flow of logic synthesis, with simple inter-connect wire-load models, followed by physical synthesis does not work anymore. This has resulted in multiple itera-tions, with feedback, of this flow, with no promise of con-vergence. This is referred to as the design convergence prob-lem. In addition to this, an increase in coupling capacitance results in crosstalk, thus compromising signal integrity. While design tools offer some support (and increased ex-pense) for both of the above issues, these problems are far from being solved. Increased Complexity: The flip-side of smaller geometries is that we can now integrate more transistors on the same die. This is amplified by the fact that manufacturing advances have further increased possible die-sizes (roughly a growth of 20% every four years [2]).
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