EE1411EECS1411Lecture #2EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 2Lecture 2Integrated Circuit Basics:Integrated Circuit Basics:Manufacturing and CostManufacturing and CostEE1412EECS1412Lecture #2Administrative StuffAdministrative Stuff Discussions start this Friday We have a third GSI Richie Przybyla, rjp@eecs OH: Wed. 4-5pm Lab: Tues. 12:30-3:30pm Labs start next week Homework #1 is due this Thursday Everyone should have an EECS instructional account Use cory, quasar, pulsarEE1413EECS1413Lecture #2MTWRF89101112123456Lab(Yue)353 CoryLab(Milos)353 CoryDISC*(TBA)293 CoryDISC*(Milos)293 CoryLec(Elad)277 CoryProblemSets DueLec(Elad)277 Cory* Discussion sections will cover identical materialOH(Elad)565 CoryYour EECS141 WeekYour EECS141 WeekDISC*(Yue)293 CoryOH(Elad)565 CoryOH(Milos)TBD CoryOH(Yue)TBD CoryLab(Richie)353 CoryOH(Richie)TBD CoryEE1414EECS1414Lecture #2HSPICE SyntaxHSPICE SyntaxSimple CMOS inverter.include '/home/ff/ee141/MODELS/gpdk090_mos.sp‘ TT_s1v* netlistVdd vdd 0 1.2VIN in 0 PULSE 0 1.2 200ps 100ps 100ps 2ns 4nsM0 out in vdd vdd gpdk090_pmos1V L=100e-9 W=120e-9M1 out in gnd gnd gpdk090_nmos1V L=100e-9 W=120e-9R1 in gnd 10KR2 out vdd 100K* extra control information.options post=2 nomod* analysis.op.TRAN .01ns 3ns.DC VIN 0 1.2 .001.ENDEE1415EECS1415Lecture #2Last LectureLast Lecture Last lecture Introduction, Moore’s law, future of ICs Today’s lecture Introduce basics of integrated circuit manufacturing and cost Reading: Ch 2.1, 2.2EE1416EECS1416Lecture #2CMOS CMOS Manufacturing Manufacturing ProcessProcessEE1417EECS1417Lecture #2The MOS TransistorThe MOS TransistorPolysiliconAluminumEE1418EECS1418Lecture #2The Manufacturing ProcessThe Manufacturing Processhttp://bwrc.eecs.berkeley.edu/IcBookFor a complete walk-through of the process (64 steps), check theBook web-pageEE1419EECS1419Lecture #2oxidationopticalmaskprocessstepphotoresist coatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotoresiststepper exposuredevelopmentTypical operations in a single photolithographic cycle (from [Fullman]).PhotoPhoto--Lithographic ProcessLithographic ProcessEE14110EECS14110Lecture #2Patterning of SiOPatterning of SiO22Si-substrateSi-substrateSi-substrate(a) Silicon base material(b) After oxidation and depositionof negative photoresist(c) Stepper exposurePhotoresistSiO2UV-lightPatternedoptical maskExposed resistSiO2Si-substrateSi-substrateSi-substrateSiO2SiO2(d) After development and etching of resist,chemical or plasma etch of SiO2(e) After etching(f) Final result after removal of resistHardened resistHardened resistChemical or plasmaetchEE14111EECS14111Lecture #2Advanced MetallizationAdvanced MetallizationEE14112EECS14112Lecture #2A Modern CMOS ProcessA Modern CMOS Processp-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2DualDual--Well ShallowWell Shallow--TrenchTrench--Isolated CMOS ProcessIsolated CMOS ProcessEE14113EECS14113Lecture #2Transistor LayoutTransistor Layoutp-wellSiO2polySiO2n+Cross-Sectional ViewLayout Viewpolyp-wellEE14114EECS14114Lecture #2CostCostEE14115EECS14115Lecture #2Cost of Integrated CircuitsCost of Integrated Circuits NRE (non-recurrent engineering) costs - fixed Independent of volume (i.e., number of units made/sold) Examples: design time and effort, mask generation, equipment, etc. Recurrent costs - variable proportional to volume Examples: silicon processing, packaging, test Most of these proportional to chip areaEE14116EECS14116Lecture #2NRE Cost is IncreasingNRE Cost is IncreasingEE14117EECS14117Lecture #2Total CostTotal Cost Cost per IC Variable costvolumecost fixed IC percost variable IC percost +=yieldtest finalpackaging ofcost test die ofcost die ofcost cost variable++=EE14118EECS14118Lecture #2Die CostDie CostSingle dieWaferyield die* waferper dies waferofcost die ofcost =From: http://www.amd.comEE14119EECS14119Lecture #2Wafer sizeWafer sizeFrom: http://www.sandpile.org8” (200mm)12” (300mm)12” (300mm)90nm CMOS90nm CMOS65nm CMOSAMD AthlonEE14120EECS14120Lecture #2YieldYield%100 waferper chips of number Total waferper chips good of No.×=Yyield Die waferper Diescost Wafercost Die×=()area die2diameter waferarea diediameter/2 wafer waferper Dies2××π−×π=EE14121EECS14121Lecture #2DefectsDefectsdefects per unit area die areadie yield 1 ,αα−×⎛⎞=+⎜⎟⎝⎠where α is approximately 3 ()()4-1 -31die cost die areadie/wafer die area yield die area∝∝⎡⎤∝∝⎣⎦Yield = 1/4Yield = 19/24EE14122EECS14122Lecture #2Cost per TransistorCost per Transistor0.00000010.00000010.0000010.0000010.000010.000010.00010.00010.0010.0010.010.010.10.1111982198219851985198819881991199119941994199719972000200020032003200620062009200920122012cost: cost: ¢¢--perper--transistortransistorFabrication cost per transistorEE14123EECS14123Lecture #2Next LectureNext Lecture CMOS transistors as switches How to build an inverter Design
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