EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 8Lecture 8Inverter Delay and PowerInverter Delay and PowerEE1412EECS141AnnouncementsAnnouncements Lab 3 this week! Lab 4 next week Homework #4 due next TuesdayEE1413EECS141Class MaterialClass Material Last lecture MOS capacitances Today’s lecture Inverter delay Power dissipation Reading (3.3.2, 5.4, 5.5)EE1414EECS141Propagation DelayPropagation DelayEE1415EECS1410 0.5 1 1.5 2 2.5x 10-10-0.500.511.522.53t (sec)Vout(V)Transient ResponseTransient ResponsetpHL= 0.69 CLReqntpLH= 0.69 CLReqptpLHtpHLEE1416EECS141Design for PerformanceDesign for Performance Increase transistor widths Watch out for self-loading! Loads the following gate! Keep capacitances small Especially parasitic ones Increase VDDEE1412EE1417EECS141Delay as a function of VDelay as a function of VDDDD0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.411.522.533.544.555.5VDD(V)tp(normalized)EE1418EECS1412 4 6 8 10 12 1422.22.42.62.833.23.43.63.8x 10-11Stp(sec)Device SizingDevice Sizing(for fixed load)Self-loading effect:Intrinsic capacitancesdominateEE1419EECS1411 1.5 2 2.5 3 3.5 4 4.5 533.544.55x 10-11βtp(sec)NMOS/PMOS ratioNMOS/PMOS ratiotpLHtpHLtpβ = Wp/WnEE14110EECS141Impact of Rise Time on DelayImpact of Rise Time on DelaytpHL(nsec)0.350.30.250.20.15trise (nsec)10.80.60.40.20tp= tstep(i)+ ηtstep(i-1)EE14111EECS141CMOS Inverter CMOS Inverter Power DissipationPower DissipationEE14112EECS141Where Does Power Go in CMOS?Where Does Power Go in CMOS? Switching power Charging capacitors Leakage power Transistors are imperfect switches Short-circuit power Both pull-up and pull-down on during transition Static currents Biasing currents, in e.g. memoryEE1413EE14113EECS141Dynamic Power ConsumptionDynamic Power Consumption() ()∫∫∫====→DDVDDLoutLDDTTDDDDDDVCdvCVdttiVdttPE020010() ()∫∫∫====DDVDDLoutoutLTTLoutCCVCdvvCdttivdttPE020021iL210 DDLVCE =→VinVoutCLVDDEE14114EECS141Dynamic Power ConsumptionDynamic Power Consumption One half of the energy from the supply is consumed in the pull-up network and one half is stored on CL Energy from CLis dumped during the 1→0 transition210 DDLVCE =→221DDLRVCE =iLVinVoutCLVDD221DDLCVCE =EE14115EECS141CLVddVddVdd-VThCircuits with Reduced SwingCircuits with Reduced Swing()ThDDDDLVVVCE −=→10EE14116EECS141Dynamic Power ConsumptionDynamic Power ConsumptionPower = Energy/transition • Transition rate= CLVDD2• f0→1= CLVDD2• f • P0→1= CswitchedVDD2• f Power dissipation is data dependent –depends on the switching probability Switched capacitance Cswitched= CL• P0→1EE14117EECS141Transition Activity and PowerTransition Activity and Power Energy consumed in N cycles, EN:EN= CL• VDD2• n0→1n0→1 – number of 0→1 transitions in N cyclesfVCNnfNEPDDLNNNavg⋅⋅⋅⎟⎠⎞⎜⎝⎛=⋅=→∞→∞→210limlimfNnN⋅=→∞→→1010limαfVCPDDLavg⋅⋅⋅=→210αEE14118EECS141Short Circuit CurrentShort Circuit Current Short circuit current is usually well controlled0 20−0.500.511.522.540 60Isc (A)x 10−4CL = 20 fFCL = 100 fFCL = 500 fFtime (s)VinVoutCLVDDIsc∼ 0VinVoutCLVDDIsc= IMAXLarge loadSmall loadEE1414EE14119EECS141Transistor LeakageTransistor Leakage Transistors that are supposed to be off -leakInput at VDDInput at 0VDD0VVDDILeakVDD0VVDDILeakEE14120EECS141Np+p+Reverse Leakage Current+-VddGATEIDL = JS × AJS = 10-100 pA/μm2 at 25 deg C for 0.25μm CMOSJS doubles for every 9 deg C!Much smaller than transistor leakage in deep submicronDiode LeakageDiode LeakageEE14121EECS141The SubThe Sub--Micron MOS TransistorMicron MOS Transistor Subthreshold Conduction Threshold VariationsEE14122EECS141SubSub--Threshold ConductionThreshold Conduction0 0.5 1 1.5 2 2.510-1210-1010-810-610-410-2VGS(V)ID(A)VTLinearExponentialQuadraticTypical values for S:60 .. 100 mV/decadeThe Slope FactoroxDnkTqVDCCneIIGS+=1 ,~0S is ΔVGSfor ID2/ID1=10EE14123EECS141Transistor LeakageTransistor Leakage-9-8-7-6-5-4-30 0.2 0.4 0.6 0.8 1 1.2VGS [V]log IDS [log A]Subthreshold slope S = kT/q ln10 (1+Cd/Ci)Drain leakage current is exponential with VGSVDS= 1.2VGSDSubCiCdEE14124EECS141Transistor LeakageTransistor LeakageTwo effects:• diffusion current (like a bipolar transistor)• exponential increase with VDS(DIBL)3-10x in currenttechnologies00 0.2 0.4 0.6 0.8 1 1.2 1.4VdS[V]IDS[nA]⎟⎟⎟⎠⎞⎜⎜⎜⎝⎛−=−kTDSqVnkTGSqVDeeII 10EE1415EE14125EECS141Threshold VariationsThreshold VariationsVTLLong-channel thresholdLow VDSthresholdThreshold as a function of the length (for low VDS) Drain-induced barrier lowering (DIBL) (for short L) VDSVTEE14126EECS141Next LectureNext Lecture Buffer
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