Digital Integrated Circuits © Prentice Hall 2000Sequential LogicEECS 141 – F00Sequential LogicDigital Integrated Circuits © Prentice Hall 2000Sequential LogicAdministrivia Project Phase 1 due tomorrow Friday at5pm Homework 7 due next Tu Discussion: time of midterm 2» Proposal 1: Th Nov 2 (original)» Proposal 2: Th Nov 9– No class next Th– Regular class on Th Nov 9 + exam in theeveningDigital Integrated Circuits © Prentice Hall 2000Sequential LogicLast Lecture Sequential Design» Latch versus Flip-flop» Positive feedback versus capacitivestorage» Definition of important parametersDigital Integrated Circuits © Prentice Hall 2000Sequential LogicToday’s Lecture Overlap insensitive structures True-single phase logic (TSPC) MultivibratorsDigital Integrated Circuits © Prentice Hall 2000Sequential LogicFlip-Flop: Timing DefinitionsDATASTABLEDATASTABLEInOuttttφtsetuptholdtpFFDigital Integrated Circuits © Prentice Hall 2000Sequential LogicDelay vs. Setup/Hold Times050100150200250300350-200 -150 -100 -50 0 50 100 150 200Data-Clk [ps]Clk-Output [ps]Setup HoldMinimum Data-OutputDigital Integrated Circuits © Prentice Hall 2000Sequential LogicMaximum Clock FrequencyFF’sLOGICtp,combφAlso:tcdreg+tcdlogic>tholdtcd: contamination delay =minimum delayDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPulse-Triggered LatchesMaster-SlaveLatchesDClkQ DClkQClkDataDClkQClkDataPulse-TriggeredLatchL1 L2 LFlip-flops:Digital Integrated Circuits © Prentice Hall 2000Sequential LogicPropagation Delay Based Edge-TriggeredφInXN2N1OutφInXOuttpLH= Mono-Stable Multi-VibratorDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPulse-Triggered LatchesClkDQQSR7474, SR latch as a second stageDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPulse-Triggered LatchesFirst stage is a senseamplifier, precharged tohigh, when Clk =0After rising edge of theclock sense amplifiergenerates the pulse onS or RThe pulse is captured inS-R latchSense-amplifier-based flip-flop, DEC Alpha 21264, StrongARM 110Digital Integrated Circuits © Prentice Hall 2000Sequential LogicFlip-flop insensitive to clock overlapDInφφφφVDDVDDM1M3M4M2 M6M8M7M5φ−sectionφ−sectionCL1CL2XC2MOS LATCHDigital Integrated Circuits © Prentice Hall 2000Sequential LogicC2MOS avoids Race ConditionsDIn1M1M3M2M6M7M51DInVDDVDDM1M4M2 M6M8M500VDDVDD(a) (1-1) overlap (b) (0-0) overlapXXDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPipeliningREGφREGφREGφlog.REGφREGφREGφ.REGφREGφlogOut OutababNon-pipelined versionPipelined versionDigital Integrated Circuits © Prentice Hall 2000Sequential LogicPipelined Logic using C2MOSInFOutφφVDDφφVDDφφVDDC2C1GC3NORA CMOSWhat are the constraints on F and G?Digital Integrated Circuits © Prentice Hall 2000Sequential LogicExample1φφVDDφφVDDVDDNumber of a static inversions should be evenDigital Integrated Circuits © Prentice Hall 2000Sequential LogicNORA CMOS ModulesφφVDDVDDPDNφIn1In2In3φVDDPUNφφOutφφVDDOutVDDPDNφIn1In2In3φVDDIn4In4VDD(a) φ-module(b) φ-moduleCombinational logic LatchDigital Integrated Circuits © Prentice Hall 2000Sequential LogicTSPC-TrueSinglePhaseClockLogicM1M2M3VDDInOutφφM1M2M3VDDInOutφφM1M2M3VDDInOutφM1M2M3VDDInOutφPrecharged NPrecharged PNon-precharged NNon-precharged PDigital Integrated Circuits © Prentice Hall 2000Sequential LogicDoubled TSPC LatchesφVDDOutφVDDDoubled n-TSPC latchInφVDDOutφVDDDoubled p-TSPC latchInDigital Integrated Circuits © Prentice Hall 2000Sequential LogicTSPC-TrueSinglePhaseClockLogicφVDDOutφVDDφVDDφVDDInStaticLogicPUNPDNIncluding logic intothe latchInserting logic betweenlatchesDigital Integrated Circuits © Prentice Hall 2000Sequential LogicMaster-Slave TSPC Flip-flopsφVDDDVDDφVDDDφVDDφVDDDVDDφφDφVDDφVDDDVDDφφD(a) Positive edge-triggeredDflip-flop (b) Negative edge-triggeredDflip-flop(c) Positive edge-triggeredDflip-flopusing split-output latchesXYDigital Integrated Circuits © Prentice Hall 2000Sequential LogicLatches versus RegistersCLKQDCLKQDclkInOutGIn OutInOutPositive Latch Negative LatchGclkInOutOutstableOutfollows InOutstableOutfollowsInLatch: level-sensitive circuit passing the input to the outputwhen the latch is enabled - otherwise it is in holdEdge-triggered register: samples the input on clock transitionDigital Integrated Circuits © Prentice Hall 2000Sequential LogicOther Flip-FlopsQJKQφTφQJKQφφDQQφTQQφDToggle Flip-FlopDelay Flip-FlopDigital Integrated Circuits © Prentice Hall 2000Sequential LogicSchmitt TriggerIn OutVinVoutVOHVOLVM–VM+•VTC with hysteresis•Restores signal slopesDigital Integrated Circuits © Prentice Hall 2000Sequential LogicNoise Suppression usingSchmitt TriggerVM+VM–VoutVinttt0t0 + tpDigital Integrated Circuits © Prentice Hall 2000Sequential LogicCMOS Schmitt TriggerVDDVinVoutM1M2M3M4XMoves switching thresholdof first inverterDigital Integrated Circuits © Prentice Hall 2000Sequential LogicSchmitt TriggerSimulated VTC0.0 1.0 2.0 3.0 4.0 5.0Vin (V)0.01.02.03.04.05.0VX (V)0.0 1.0 2.0 3.0 4.0 5.0Vin (V)0.02.04.06.0Vout (V)VM-VM +Digital Integrated Circuits © Prentice Hall 2000Sequential LogicCMOS Schmitt Trigger (2)InVDDVDDOutM1M2M3M4M5M6XDigital Integrated Circuits © Prentice Hall 2000Sequential LogicMultivibrator CircuitsBistable MultivibratorMonostable MultivibratorAstable Multivibratorflip-flop, Schmitt Triggerone-shotoscillatorSRTDigital Integrated Circuits © Prentice Hall 2000Sequential LogicTransition-Triggered MonostableDELAYtdInOuttdDigital Integrated Circuits © Prentice Hall 2000Sequential LogicMonostable Trigger (RC-based)VDDInOutABCRInBOuttVMt2t1(a)Trigger circuit.(b) Waveforms.Digital Integrated Circuits © Prentice Hall 2000Sequential LogicAstable Multivibrators (Oscillators)012 N-1012345t(nsec)-1.01.03.05.0V (Volt)V1V3V5Ring Oscillatorsimulated response of 5-stage oscillatorDigital Integrated Circuits © Prentice Hall 2000Sequential LogicVoltage Controller Oscillator (VCO)InVDDM3M1M2M4M5VDDM6VcontrCurrent starved inverterIrefIrefSchmitt Triggerrestores signal slopes0.5 1.5 2.5Vcontr(V )0.0246tpHL(nsec)propagation delay as a functionof control voltageDigital Integrated Circuits © Prentice Hall 2000Sequential LogicRelaxation OscillatorOut2CROut1IntI1I2T = 2 (log3)
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