EE1411EECS1411Lecture #5EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 5Lecture 5Overview of SemiconductorOverview of SemiconductorMemoryMemoryEE1412EECS1412Lecture #5AnnouncementsAnnouncements Please use the news group to ask questions Don’t need a new program: try http://groups.google.com For additional questions, send emails to ee141@cory Reaches entire teaching staff Homework #2 due today Homework #3 due next Thursday Labs start tomorrowEE1413EECS1413Lecture #5Class MaterialClass Material Last lecture Detailed Switch Model CMOS Gates Design Rules Today’s lecture Overview of semiconductor memory Reading (Chapter 12.1, 12.2.3, 12.3.1)EE1414EECS1414Lecture #5Semiconductor Semiconductor MemoryMemoryEE1415EECS1415Lecture #5Why Memory?Why Memory?Intel 45nm Core 2EE1416EECS1416Lecture #5Semiconductor Memory ClassificationSemiconductor Memory ClassificationRead-Write MemoryNon-VolatileRead-WriteMemoryRead-Only MemoryEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFOEE1417EECS1417Lecture #5Random Access Memories (RAM)Random Access Memories (RAM) STATIC (SRAM) DYNAMIC (DRAM)Data stored as long as supply is appliedLarger (6 transistors/cell)FastDifferential (usually)Periodic refresh requiredSmaller (1-3 transistors/cell)SlowerSingle EndedEE1418EECS1418Lecture #5Random Access Chip ArchitectureRandom Access Chip Architecture Conceptual: linear array Each box holds some data But this does not lead to a nice layout shape Too long and skinny Create a 2-D array Decode Row and Column address to get dataEE1419EECS1419Lecture #5Basic Memory ArrayBasic Memory ArrayCORE:- keep square within a 2:1 ratio- rows are word lines- columns are bit linesDECODERS:- needed to reduce total numberof pins; N+M address lines for2N+M bits of storageEx: if N+M=20220= 1MbMULTIPLEXING:- used to select one or morecolumns for input or outputof data- data in and out on columnsEE14110EECS14110Lecture #5Basic Static Memory ElementBasic Static Memory Element• If D is high, D_b will be driven low• Which makes D stay high• Positive feedbackEE14111EECS14111Lecture #5Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1Vo2Vo2 =Vi1Vo1=Vi2Vo1Vi25Vo1Vi25Vo1Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1EE14112EECS14112Lecture #5Writing into a CrossWriting into a Cross--Coupled PairCoupled PairAccess transistor must be able to overpower the feedbackEE14113EECS14113Lecture #5Writing a Writing a ““11””EE14114EECS14114Lecture #5Memory CellMemory CellComplementary data values are written (read) from two sidesEE14115EECS14115Lecture #5SRAM ColumnSRAM ColumnWL2WL0WL3BLBL_BEE14116EECS14116Lecture #5SRAM Array LayoutSRAM Array LayoutEE14117EECS14117Lecture #565nm SRAM65nm SRAM ST/Philips/MotorolaAccess TransistorPull downPull upEE14118EECS14118Lecture #5DecodersDecodersWord 0Word 1Word 2Word N22Word N21StoragecellM bits M bitsNwordsS0S1S2SN22A0A1AK21K=log2NSN21Word 0Word 1Word 2Word N22Word N21StoragecellS0Input-Output(M bits)Intuitive architecture for N x M memoryToo many select signals:N words == N select signalsK = log2NDecoder reduces the number of select signalsInput-Output(M bits)DecoderEE14119EECS14119Lecture #5Row DecodersRow DecodersCollection of 2Mcomplex logic gatesOrganized in regular and dense fashion(N)AND DecoderNOR DecoderEE14120EECS14120Lecture #5Decoder Design ExampleDecoder Design Example Look at decoder for 256x256 memory block (8KBytes)EE14121EECS14121Lecture #5Problem SetupProblem Setup Goal: Build fastest, lowest possible power decoder with static CMOS logic What we know Basically need 256 AND gates, each one of them drives one word lineN=8EE14122EECS14122Lecture #5Possible AND8Possible AND8 Build 8-input NAND gate using 2-input gates and inverters Is this the best we can do? Is this better than using fewer NAND4 gates?EE14123EECS14123Lecture #5Possible DecoderPossible Decoder 256 8-input AND gates Each built out of tree of NAND gatesand inverters Need to drive a lotof capacitance (SRAMcells) What’s the best way to do this?EE14124EECS14124Lecture #5Next LectureNext Lecture Buffer delay
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