EE1411EECS1411Lecture #4EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 4Lecture 4CMOS Switches and GatesCMOS Switches and GatesDesign RulesDesign RulesEE1412EECS1412Lecture #4Administrative StuffAdministrative Stuff Labs start this week Software lab #2 starts Friday Lab reports due the following week in lab Homework #2 due this Thurs. Homework #3 out this Thurs.EE1413EECS1413Lecture #4Review: Review: VTCsVTCsEE1414EECS1414Lecture #4Review: DelayReview: Delay Is it possible for a gate to have negative delay?EE1415EECS1415Lecture #4Review: EnergyReview: Energy Pulsed inverterEE1416EECS1416Lecture #4Class MaterialClass Material Last lecture Transistor as a switch, inverter Design metrics Today’s lecture Detailed switch model CMOS gates (intro to Ch. 3, 6) Design rules (Ch. 2.3) Reading (2.3, 3.3.1-3.3.2, 6.1-6.2.1)EE1417EECS1417Lecture #4Switch Model of MOS TransistorSwitch Model of MOS Transistor|VGS|SDG|VGS| < |VT||VGS| > |VT|RonSDSDEE1418EECS1418Lecture #4MOS Switch Model (Capacitance)MOS Switch Model (Capacitance)EE1419EECS1419Lecture #4Switch Model (Width)Switch Model (Width)EE14110EECS14110Lecture #4CMOS Inverter ModelCMOS Inverter ModelVinVoutCLVDDEE14111EECS14111Lecture #4CMOS LogicCMOS LogicEE14112EECS14112Lecture #4The CMOS Inverter: A First GlanceThe CMOS Inverter: A First GlanceVinVoutCLVDDEE14113EECS14113Lecture #4Static CMOS GatesStatic CMOS GatesAt every point in time (except during the switchingtransients) each gate output is connected to eitherVDDor VSSvia a low resistive path.The outputs of the gates assume at all times the valueof the Boolean function implemented by the circuit(ignoring, once again, the transient effects during switching periods).(Will contrast this later to dynamic circuit style.)EE14114EECS14114Lecture #4Static Complementary CMOSStatic Complementary CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPMOS onlyNMOS onlyPUN and PDN are dual logic networksPUN and PDN functions are complementary ……EE14115EECS14115Lecture #4Threshold DropsThreshold DropsVDDVDD→ 0PDN0 → VDDCLCLPUNVDD0 → VDD-VTnCLVDDVDDVDD→ |VTp|CLSDSDVGSSSDDVGSEE14116EECS14116Lecture #4NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel ConnectionY = X if A AND BY = X if A OR B Transistor ↔ switch controlled by its gate signal NMOS switch closes when switch control input is high NMOS transistors pass a “strong” 0 but a “weak” 1ABXYXYABAND OREE14117EECS14117Lecture #4PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection PMOS switch closes when switch control is low PMOS transistors pass a “strong” 1 but a “weak” 0XYABABXYNOR NAND Y = X if A AND B = A + BY = X if A OR B = ABEE14118EECS14118Lecture #4Complementary CMOS Logic StyleComplementary CMOS Logic Style PUP is the dual to PDN(can be shown using DeMorgan’s Theorems) Static CMOS gates are always invertingA + B = ABAB = A + BAND = NAND + INVEE14119EECS14119Lecture #4Example Gate: NANDExample Gate: NAND PDN: G = AB ⇒ Conduction to GND PUN: F = A + B = AB ⇒ Conduction to VDD G(In1,In2,In3,…) ≡ F(In1,In2,In3,…)EE14120EECS14120Lecture #4Example Gate: NORExample Gate: NOREE14121EECS14121Lecture #4Complex CMOS GateComplex CMOS GateOUT = D + A • (B + C)DABCDABCEE14122EECS14122Lecture #4CMOS PropertiesCMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipationEE14123EECS14123Lecture #4Design RulesDesign RulesEE14124EECS14124Lecture #4Transistor LayoutTransistor Layoutp-wellSiO2polySiO2n+Cross-Sectional ViewLayout Viewpolyp-wellEE14125EECS14125Lecture #4CMOS Process LayersCMOS Process LayersLayerPolysiliconMetal1Metal2Contact To PolyContact To DiffusionViaWell (p,n)Active Area (n+,p+)Color RepresentationYellowGreenRedBlueMagentaBlackBlackBlackWell contact (p+,n+)GreenEE14126EECS14126Lecture #4Layers in 0.25 Layers in 0.25 µµm CMOS processm CMOS process(well contacts)EE14127EECS14127Lecture #4Design RulesDesign Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)EE14128EECS14128Lecture #4Design RulesDesign Rules Intra-layer Widths, spacing, area Inter-layer Enclosures, distances, extensions, overlaps Special rules (sub-0.25µm) Antenna rules, density rules, (area)EE14129EECS14129Lecture #4IntraIntra--Layer Design RulesLayer Design RulesMetal2431090 WellActive33Polysilicon22Different PotentialSame PotentialMetal1332Contactor ViaSelect2or62HoleEE14130EECS14130Lecture #4InterInter--Layer: Transistor LayoutLayer: Transistor Layout1253TransistorEE14131EECS14131Lecture #4InterInter--Layer: Layer: ViasViasand Contactsand Contacts121ViaMetal toPoly ContactMetal toActive Contact1254322EE14132EECS14132Lecture #4InterInter--Layer: Well and SubstrateLayer: Well and Substrate133222WellSubstrateSelect35EE14133EECS14133Lecture #4CMOS Inverter LayoutCMOS Inverter LayoutAA’np-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-A’AA’EE14134EECS14134Lecture #4Layout EditorLayout EditorEE14135EECS14135Lecture #4Design Rule CheckerDesign Rule CheckerEE14136EECS14136Lecture #4Sticks DiagramSticks Diagram13InOutVDDGNDStick diagram of inverter• Dimensionless layout entities• Only topology is importantEE14137EECS14137Lecture #4Circuit Under DesignCircuit Under DesignVDDVDDVinVoutM1M2M3M4Vout2EE14138EECS14138Lecture #4CMOS InverterCMOS InverterPolysiliconInOutVDDGNDPMOS2λMetal 1NMOSOutInVDDPMOSNMOSContactsN WellEE14139EECS14139Lecture #4Two InvertersTwo InvertersConnect in MetalShare power and groundAbut cellsVDDEE14140EECS14140Lecture #4Next LectureNext Lecture Overview of semiconductor
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