1EE141 – Fall 2005Lecture 4The MOS TransistorThe MOS TransistorMOS Transistor ModelMOS Transistor ModelEE141 2Important! Discussions and Labs start next week! You must show up in one of the lab sessionsnext week• If you don’t show up you will be dropped from the class (unless you let me know that you still want to be in the class) Homework 2 due next Thursday, September 152EE141 3TAmtng* Discussion sessions will cover identical materialMonTueWedThuFriLec(Dejan)203 McLaughlinLec(Dejan)203 McLaughlinOH(Dejan)511 CoryDISC*(Ke)203 McLaughlin910111212345 67Lab(Louis)353 CoryLab(Louis)353 CoryOH(Ke)197 CoryOH(Lynn)197 CoryProblemSets DueLab - NEW(Lynn)353 CoryLab (Ke) 353 CoryDISC*(Lynn)293 CoryYour EE141 Week at a GlanceEE141 4Agenda Last Lecture• Design metrics• MOS manufacturing process• Design rules Today’s Lecture• Basic MOS transistor operation• Large-signal MOS model for manual analysis• The CMOS inverter at a first glance3EE141 5The MOS TransistorPolysilicon AluminumEE141 6Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width• Scalable design rules: lambda parameter• Absolute dimensions (micron rules)4EE141 7CMOS Process LayersLayerPolysiliconMetal1Metal2Contact To PolyContact To DiffusionViaWell (p,n)Active Area (n+,p+)Color RepresentationYellowGreenRedBlueMagentaBlackBlackBlackSelect (p+,n+)GreenEE141 8Layers in 0.25µm CMOS Process5EE141 9Design Rules Intra-layer: widths, spacing Inter-layer: enclosures, overlaps• Transistor rules• Contact and via rules• Well and substrate contacts Special rules (sub-0.25µm)• Area, antenna rules, density rulesEE141 10Intra-Layer Design RulesMetal2431090 WellActive33Polysilicon22Different PotentialSame PotentialMetal1332Contactor ViaSelect2or62Hole6EE141 111253TransistorInter Layer: Transistor RulesTransistorEE141 12Inter Layer: Vias and Contacts121ViaMetal toPoly ContactMetal toActive Contact12543227EE141 13133222WellSubstrateSelect35Inter Layer: Well and SubstrateEE141 14Example: CMOS Inverter LayoutAA’np-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-A’AA’8EE141 15Layout Editor – MicroMagicEE141 16Layout Editor –Cadence VirtuosoIn1 In2Outvddgnd9EE141 17Design Rule Checkerpoly_not_fet to all_diff minimum spacing = 0.14 um.EE141 18Sticks Diagram13InOutVDDGNDStick diagram of inverter• Dimensionless layout entities• Only topology is important10EE141 19OutlineMOS TransistorMOS Transistor• Basic Operation• Modes of Operation• Deep sub-micron MOSCMOS InverterCMOS InverterEE141 20What is a Transistor?|VGS|A MOS Transistor|VGS| ≥ |VT|SDRonA Switch!SDG11EE141 21Switch Model of CMOS Transistor|VGS|SDG|VGS| < |VT||VGS| > |VT|RonSDSDEE141 22NMOS and PMOSVGS> 0SDGVGS< 0SDGNMOS Transistor PMOS Transistor12EE141 23SDGBSDGSDGSDGNMOS Enhancement NMOS DepletionPMOS EnhancementNMOS withBulk ContactMOS Transistors:Types and SymbolsEE141 24OutlineMOS TransistorMOS Transistor• Basic Operation• Modes of Operation• Deep sub-micron MOSCMOS InverterCMOS Inverter13EE141 25n+p-substrateDSGBVGS+–Depletionregionn-c hanne ln+Threshold Voltage: ConceptEE141 26The Threshold Voltage()FSBFTTVVVφφγ220−+⋅+=iATFnNln⋅=φφ Threshold Fermi potential2ΦFis approximately −0.6V for p-type substratesγ is the body factorVT0is approximately 0.45V for our process14EE141 27The Body Effect-2.5 -2 -1.5 -1 -0.5 00.40.450.50.550.60.650.70.750.80.850.9VBS (V)VT (V)VT0reverse body biasEE141 28The Drain Current[]TGSoxiVxVVCxQ−−⋅−= )()(oxoxoxtCε= Charge in the channel is controlled by the gate voltage: Drain current is proportional to charge and velocity:WxQxIinD⋅⋅−= )()(υdxdVxxnnn⋅=⋅−=µξµυ)()(15EE141 29The Drain Current()dVVVVWCdxITGSoxnD⋅−−⋅⋅⋅=⋅µ Combining velocity and charge: Integrating over the channel:()−⋅−⋅⋅=22DSDSTGSnDVVVVLWkI’Transconductance:oxoxnoxnntCkεµµ⋅=⋅=’EE141 30OutlineMOS TransistorMOS Transistor• Basic Operation• Modes of Operation• Deep sub-micron MOSCMOS InverterCMOS Inverter16EE141 31n+n+p-substrateDSGBVGSxLV(x)+–VDSIDTransistor in Linear ModeVGS> VDS+ VTEE141 32n+n+SGVGSDVDS > VGS - VTVGS - VT+-Transistor in SaturationPinch-offVT< VGS< VDS+ VT17EE141 33Saturation For VGD< VT, the drain current saturates:()22TGSnDVVLWkI −⋅⋅=’ Including channel-length modulation:()( )DSTGSnDVVVLWkI ⋅+⋅−⋅⋅=λ122’CLMEE141 34Modes of OperationCutoff:VGS< VTResistive:VGS> VDS+VTSaturation:VT< VGS< VDS+ VT ()−⋅−⋅⋅=22DSDSTGSnDVVVVLWkI’()22TGSnDVVLWkI −⋅⋅=’0=DI18EE141 35QuadraticRelationship0 0.5 1 1.5 2 2.50123456x 10-4VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistive SaturationVDS= VGS-VTCurrent-Voltage Relations:A Good Ol’ TransistorVDS(V)ID(A)EE141 36A Model for Manual AnalysisSDGID()−⋅−⋅⋅=22DSDSTGSnDVVVVLWkI’()( )DSTGSnDVVVLWkI ⋅+⋅−⋅⋅=λ122’()FSBFTTVVVφφγ220−+⋅+=VDS> VGS– VTVDS< VGS– VTwith19EE141 37OutlineMOS TransistorMOS Transistor• Basic Operation• Modes of Operation• Deep sub-micron MOSCMOS InverterCMOS InverterEE141 38LinearRelationship-40 0.5 1 1.5 2 2.500.511.522.5x 10VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VEarlySaturationCurrent-Voltage Relations:The Deep Sub-Micron EraVDS(V)ID(A)20EE141 39Velocity Saturationξ(V/µm)ξc= 1.5υn(m/s)υsat= 105Constant mobility (slope = µ)Constant velocity Velocity saturates due to carrier scattering effectsEE141 40Velocity SaturationIDLong-channel deviceShort-channel deviceVDSVDSATVGS-VTVGS = VDD21EE141 41IDversus VGS0 0.5 1 1.5 2 2.5012456x 10-4Long ChannelShort ChannelquadraticlinearquadraticVGS(V)ID(A)3EE141 42Regions of Operation-40 0.5 1 1.5 2 2.500.511.522.5x 10VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 V0 0.5 1 1.5 2 2.50123456x 10-4VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistive SaturationVDS= VGS-VTVDS(V) VDS(V)ID(A)ID(A)ResistiveVelocitySaturationLong Channel(L=10µm)Short Channel(L=0.25µm)W/L=1.522EE141 43Including Velocity Saturationcnξξξµυ+⋅=1In deep submicron, there are four regions of operation:(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation Approximate velocity:satυυ=for ξ≤ξcfor ξ≥ξc And integrate current again:()()−⋅−⋅⋅⋅+⋅=212DSDSTGScDSoxnDVVVVLWLVCIξµEE141
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