EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 23Lecture 23Sequential LogicSequential LogicTimingTimingEE1412EECS141AnnouncementsAnnouncements Homework 8 due on Thursday Project phase three in lab this week Project reports due on Monday Poster presentations next weekEE1412EE1413EECS141Class MaterialClass Material Last lecture Latches and registers Today’s lecture Finish sequential logic Timing Reading Chapter 7, 10EE1414EECS141Other Other Sequential Sequential CircuitsCircuitsEE1413EE1415EECS141Other Sequential CircuitsOther Sequential Circuits Schmitt Trigger Monostable Multivibrators Astable MultivibratorsEE1416EECS141Schmitt TriggerSchmitt TriggerIn OutVinVou tVOHVOLVM–VM+•VTC with hysteresis•Restores signal slopesEE1414EE1417EECS141Noise Suppression using Schmitt TriggerNoise Suppression using Schmitt TriggerEE1418EECS141CMOS Schmitt TriggerCMOS Schmitt TriggerMoves switching thresholdof the first inverter VinM2M1VDDXVoutM4M3EE1415EE1419EECS1412.5VX(V)VM2VM1Vin(V)VCT with hysteresis2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.52.5Vx(V)k= 2k= 3k= 4k= 1Vin(V)2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.5The effect of varying the ratio of the PMOS device M4. The width is k*0.5μm.Schmitt Trigger: Simulated VTCSchmitt Trigger: Simulated VTCEE14110EECS141CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)VDDVDDOutInM1M5M2XM3M4M6EE1416EE14111EECS141Bistable MultivibratorMonostable MultivibratorAstable Multivibratorflip-flop, Schmitt Triggerone-shotoscillatorSRTMultivibratorMultivibratorCircuitsCircuitsEE14112EECS141DELAYtdInOuttdTransitionTransition--Triggered MonostableTriggered MonostableEE1417EE14113EECS141VDDInOutABCRInBOuttVMt2t1(a) Trigger circuit.(b) Waveforms.Monostable Triggered (RCMonostable Triggered (RC--based)based)EE14114EECS141Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)012 N-1simulated response of 5-stage oscillatorEE1418EE14115EECS141Timing Timing DefinitionsDefinitionsEE14116EECS141Synchronous TimingSynchronous TimingCombinationalLogicR1R2CinCoutOutInCLKEE1419EE14117EECS141Latch ParametersLatch ParametersDClkQDQClktc-qtholdPWmtsutd-qDelays can be different for rising and falling data transitionsTEE14118EECS141Register ParametersRegister ParametersDClkQDQClktc-qtholdTtsuDelays can be different for rising and falling data transitionsEE14110EE14119EECS141R1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc − qtc − q, cdtsu, tholdtlogictlogic, cdCycle time: TClk> tc-q+ tlogic+ tsuRace margin: thold< tc-q,cd+ tlogic,cdTiming Constraints Timing Constraints EE14120EECS141Clock Clock NonidealitiesNonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clockingEE14111EE14121EECS141Clock UncertaintiesClock Uncertainties243Power SupplyInterconnect5Temperature6Capacitive Load7Coupling to Adjacent Lines1Clock GenerationDevicesSources of clock uncertaintyEE14122EECS141Clock Skew and JitterClock Skew and Jitter Both skew and jitter affect the effective cycle time Only skew affects the race marginClkClktSKtJSEE14112EE14123EECS141Clock SkewClock Skew# of registersClk delayInsertion delayMax Clk skewEarliest occurrenceof Clk edgeNominal –δ/2Latest occurrenceof Clk edgeNominal + δ/2δEE14124EECS141Positive and Negative SkewPositive and Negative SkewR1In(a) Positive skewCombinationalLogicDQtCLK1CLKdelaytCLK2R2DQCombinationalLogictCLK3R3•••DQdelayR1In(b) Negative skewCombinationalLogicDQtCLK1delaytCLK2R2DQCombinationalLogictCLK3R3•••DQdelay CLKEE14113EE14125EECS141Positive SkewPositive SkewCLK1CLK2TCLKδTCLK+δ+ thδ2143Launching edge arrives before the receiving edgeEE14126EECS141Negative SkewNegative SkewReceiving edge arrives before the launching edgeCLK1CLK2TCLKδTCLK-δ2143EE14114EE14127EECS141Timing ConstraintsTiming ConstraintsR1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc − qtc − q, cdtsu, tholdtlogictlogic, cdMinimum cycle time:T -δ= tc-q+ tsu+ tlogicWorst case is when receiving edge arrives early (positive δ)EE14128EECS141Timing ConstraintsTiming ConstraintsR1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc − qtc − q, cdtsu, tholdtlogictlogic, cdHold time constraint:t(c-q, cd)+ t(logic, cd)> thold+ δWorst case is when receiving edge arrives lateRace between data and clockEE14115EE14129EECS141Longest Logic Path in Longest Logic Path in EdgeEdge--Triggered SystemsTriggered SystemsClkTTSUTClk-QTlogicLatest point of launchingEarliest arrivalof next cycleTJS + δEE14130EECS141Clock Constraints in Clock Constraints in EdgeEdge--Triggered SystemsTriggered SystemsIf launching edge is late and receiving edge is early, the data will not be too late if:Minimum cycle time is determined by the maximum delays through the logicTc-q+ Tlogic+ TSU< T – TJS,1–TJS,2-δTc-q+ Tlogic+ TSU+ δ+ 2 TJS< TSkew can be either positive or negativeEE14116EE14131EECS141Shortest PathShortest PathClkTclk-q,cdTlogic, cdEarliest point of launchingData must not arrivebefore this timeClkTHNominalclock edgeEE14132EECS141Clock Constraints Clock Constraints in Edgein Edge--Triggered SystemsTriggered SystemsMinimum logic delay If launching edge is early and receiving edge is late:Tc-q, cd+ Tlogic, cd–TJS,1< TH+ TJS,2+ δTc-q, cd+ Tlogic, cd< TH+ 2TJS+ δEE14117EE14133EECS141How to counter Clock Skew?How to counter Clock Skew?REGφREGφREGφ.REGφlogOutInClock DistributionPositive SkewNegative SkewData and Clock RoutingEE14134EECS141Register Register ––Based TimingBased TimingFlip-flopLogicφ = 1φ = 0Flip-flopdelaySkewLogic delayTSUTClk-QRepresentation after M. Horowitz, VLSI Circuits 1996.EE14118EE14135EECS141Registers and Dynamic LogicRegisters and Dynamic Logicφ = 1φ = 0Logic delayTSUTClk-Qφ = 1φ = 0Logic delayTSUTClk-QPrechargeEvaluateEvaluatePrechargeFlip-flops are used only with static logicEE14136EECS141PipeliningPipeliningREGREGREGlogaCLKCLKCLKOutbREGREGREGlogaCLKCLKCLKREGCLKREGCLKOutbReferencePipelinedEE14119EE14137EECS141LatchLatch--Based PipelineBased PipelineF GCLKCLKIn OutC1C2CLKC3CLKCLKCompute F compute GEE14138EECS141Next LectureNext Lecture Clock and power
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