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Berkeley ELENG 141 - Design Metrics

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1EE141 – Fall 2005Lecture 2Design MetricsDesign MetricsEE141 2Admin Page Everyone should have a UNIX account on Cory! This will allow you to run HSPICE!• If you do not have an account, check: http://www-inst.eecs.berkeley.edu/usr/pub/jpg/How-to-Get-Named-Acct.jpg PC accounts for 353 Cory will be created early next week (when the class list is completed) Discussions & Labs start in Week 3If you have not signed-in on the class roster,please do so after the lecture.2EE141 3Getting Started with HSPICE Run the simulator on your input file: • hspice filename.sp > filename.lis Use the waveform viewer to see the output:• awaves Musts:• Input files must have the extension .sp for the waveform viewer to work• The input file must have “.OPTIONS POST=2” specified Online help:• http://www-inst.berkeley.edu/usr/pub/HSPICE.docs/1992.2/hspice/hspice.pdf (10MB, 1953 pages, do not print!)• “The SPICE Book” by Andrei VladimirescuEE141 4Netlist Format The input files are case insensitive. The first line is always a comment. Other lines are commented with a leading * or $ All nonlinear devices must have a .MODEL statement.• Models of nonlinear elements• Circuit netlist • Control statements• Analysis3EE141 5Also Important Models: ~ee141/MODELS/g25.mod• BJT model for Homework 1: npn.mod• 0.25µm CMOS models: g25.mod Machines to log-in to• {cory, quasar, c199}.eecsEE141 6Last Lecture Last lecture• Moore’s Law• Challenges in digital IC design in the next decade Today’s lecture• Review of Moore’s Law• Design metrics4EE141 7What Happened over 30 Years?42 M transistors1.5 GHz operation1971 20002,300 transistors108 KHz operation~15,000 xComparison (automotive): Travel from San Francisco to New York in 13 sec!EE141 840048008808080858086 (P1)286 (P2)386 (P3)486 (P4)Pentium® (P5)Pentium Pro (P6)0.0010.010.111010010001970 1980 1990 2000 2010YearTransistors (MT)2X growth in 1.96 years!Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 yearsMoore’s Law in MicroprocessorsSource:S. Borkar(Intel)Pentium 45EE141 9Pentium (R)Pentium Pro (R) 486386i86011010010001.5µ1.0µ0.8µ0.6µ0.35µ0.25µ0.18µ0.13µLogic Density2x trendLogic Transistors/mm2Pentium II (R) Moore’s Law – Logic Density Shrinks and compactions meet density goals• New micro-architectures drop densitySource: IntelEE141 10Die Size Growth40048008808080858086286386486Pentium ®Pentium Pro1101001970 1980 1990 2000 2010YearDie size (mm)~7% growth per year~2X growth in 10 yearsDie size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s LawSource:S. Borkar(Intel)6EE141 11FrequencyPentium ProPentium ®486386286808680858080800840040.11101001000100001970 1980 1990 2000 2010YearFrequency (Mhz)Doubles every2 yearsSource:S. Borkar(Intel)Lead Microprocessor frequency doubles every 2 yearsLead Microprocessor frequency doubles every 2 yearsPentium 4EE141 12Processor Power386386486486Pentium(R)Pentium(R) MMXPentium Pro (R)Pentium II (R)1101001.5µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µMax Power (Watts)? Lead processor power increases every generation• Compactions provide higher performance at lower powerSource: Intel7EE141 13Power will be a Problem5KW 18KW 1.5KW 500W 40048008808080858086286386486Pentium ®0.11101001000100001000001971 1974 1978 1985 1992 2000 2004 2008YearPower (Watts)Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitiveSource:S. Borkar(Intel)Pentium ProEE141 14Productivity Trends1101001,00010,000100,0001,000,00010,000,000200319811983198519871989199119931995199719992001200520072009101001,00010,000100,0001,000,00010,000,000100,000,000Logic Tr./ChipTr./Staff Month.xxxxxxx21%/Yr. compoundProductivity growth ratex58%/Yr. compoundedComplexity growth rate10,0001,0001001010.10.010.001Logic Transistor per Chip(M)0.010.11101001,00010,000100,000Productivity(K) Trans./Staff - Mo.ComplexityComplexity outpaces design productivityComplexity outpaces design productivitySource: SematechToday8EE141 15Summary Technology scaling by 0.7 per generation• # of transistors/die doubles every 2 years• can integrate 2x more functions per chip• cost of a function decreases 2x Main problem: power delivery and dissipation How to design more and more complex chips?• Designer productivity does not double every 2 years• Need to understand different levels of abstractionEE141 16n+n+SGD+DEVICECIRCUITGATEMODULESYSTEMDesign Abstraction Levels9EE141 172010 Outlook Performance 2x / 2 years• 1 T instructions/s• 20-30 GHz clock Complexity• No of transistors: 1 Billion• Die area: 40mm x 40mm Power• 10kW!• Leakage: 1/3 of total PowerP. Gelsinger, µProcessors for the New Millennium, ISSCC 2001EE141 18OutlineDesign MetricsDesign Metrics• Cost• Reliability• Speed• Power10EE141 19Cost of Integrated Circuits NRE (Non-Recurrent Engineering) costs – fixed• design time and effort, mask generation− independent of sales volume / number of products− one-time cost factor• indirect costs (the company overhead)− R&D, manufacturing equipment etc. Recurrent costs – variable• silicon processing, packaging, test− proportional to volume− proportional to chip areaEE141 20NRE Cost is Increasing11EE141 21Total Cost Cost per IC Variable costvolumecost fixed ICper cost variable ICper cost +=yield test finalpackaging ofcost test die ofcost die ofcost cost variable++=EE141 22Die CostSingle dieWaferGoing up to 12” (30cm)yield die*per wafer dies waferofcost die ofcost =From: http://www.amd.com12EE141 23Yield%100per wafer chips ofnumber Totalper wafer chips good ofNumber ×=Yyield Dieper wafer DiescostWafer cost Die×=()area die2diameterwafer area diediameter/2wafer per wafer Dies2××π−×π=EE141 24Defectsα−α×+=area dieareaunit per defects1yield dieα≈3, complexity of mfg. processdefects per unit area = 0.5 to 1 /cm2cost of die = f (die area)413EE141 25Some Examples (1994)$4179%402961.5$15000.803Pentium$27213%482561.6$17000.703Super Sparc$14919%532341.2$15000.703DEC Alpha$7327%661961.0$13000.803HP PA 7100$5328%1151211.3$17000.804Power PC 601$1254%181811.0$12000.803486 DX2$471%360431.0$9000.902386DXDie costYieldDies/waferArea mm2Def./ cm2Wafer costLine widthMetal layersChipyield Dieper wafer DiescostWafer cost Die×=EE141 26Cost per


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Berkeley ELENG 141 - Design Metrics

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