EE1411EECS1411Lecture #6EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 6Lecture 6Inverter Delay OptimizationInverter Delay OptimizationEE1412EECS1412Lecture #6AnnouncementsAnnouncements Lab #2 Mon., Tues., Lab #3 Fri. Homework #3 due Thursday Homework #4 due next ThursdayEE1413EECS1413Lecture #6Class MaterialClass Material Last lecture Overview of Semiconductor Memory Today’s lecture Inverter Delay Optimization Reading (5.4, 5.5)EE1414EECS1414Lecture #6Inverter ChainInverter ChainCLInOut For some given CL: How many stages are needed to minimize delay? How to size the inverters? Anyone want to guess the solution?EE1415EECS1415Lecture #6Careful about Optimization Careful about Optimization ProblemsProblems Get fastest delay if build one very big inverter So big that delay is set only by self-loading Likely not the problem you’re interested in Someone has to drive this inverter…EE1416EECS1416Lecture #6Engineering Optimization Engineering Optimization Problems in GeneralProblems in General Need to have a set of constraints Constraints key to: Making the result useful Making the problem have a ‘clean’ solution For sizing problem: Need to constrain size of first inverterEE1417EECS1417Lecture #6Delay Optimization Problem #1Delay Optimization Problem #1 You are given: A fixed number of inverters The size of the first inverter The size of the load that needs to be driven Your goal: Minimize the delay of the inverter chain Need model for inverter delay vs. sizeEE1418EECS1418Lecture #6,,Psqp Nsqn WPNLLRR RR RWW⎛⎞⎛⎞=≈==⎜⎟⎜⎟⎝⎠⎝⎠tpHL= (ln 2) RNCL= tpLH= (ln 2) RpCLDelay:2WW3in gCWC=Loading on the previous stage:Inverter DelayInverter Delay Minimum length devices, L = 0.09µm Assume that for WP= 2WN= 2W approximately equal resistances, RN= RP approx. equal rise and fall delays, tpHL= tpLH Analyze as an RC network:EE1419EECS1419Lecture #6CintCLReplace ln(2) with k (a constant):Delay = kRWCint+ kRWCLDelay = kRsq,n(L/W)(3WCd) + kRsq,n(L/W)CLCN= WCgCP= 2WCg2WWInverter DelayInverter Delayint3dCWC=,WsqnLRRW⎛⎞=⎜⎟⎝⎠3in gCWC=EE14110EECS14110Lecture #6LoadDelayCintCLDelay = kRWCin(Cint/Cin+CL/Cin)= 3kLRsq,nCg[Cd/Cg + CL/(3WCg)]= Delay (Internal) + Delay (Load)CN= WCgCP= 2WCg2WWInverter with LoadInverter with LoadEE14111EECS14111Lecture #6()()()in int~/Wint LpW inLininvDelay R C CtkRCCCCC t fγ+=+=+Cint= γCin(γ≈1 for inverter)f = CL/Cin– electrical fanoutRW= Rsq(L /W);Cin=3WCgtinv= 3·ln(2)·L·RsqCgDelay FormulaDelay Formulatinvis independent of sizing of the gate!!!EE14112EECS14112Lecture #6CLIn Out12 Ntp= tp1+ tp2+ …+ tpN,1,in jpj invin jCttCγ+⎛⎞=+⎜⎟⎜⎟⎝⎠,1,,111,, NNin jppjinv inNLjiin jCttt CCCγ++==⎛⎞== + =⎜⎟⎜⎟⎝⎠∑∑Apply to Inverter ChainApply to Inverter ChainEE14113EECS14113Lecture #6Optimal Tapering for Given Optimal Tapering for Given NN,12,,1,10pinjinv invin j in j in jdt CttdC C C+−=−= Delay equation has N-1 unknowns, Cin,2… Cin,N To minimize the delay, find N-1 partial derivatives:,,1,1 ,... ...in j in jpinv invin j in jCCtt tCC+−=+ + +EE14114EECS14114Lecture #6,,1,1in j in j in jCCC−+=Optimal Tapering for Given Optimal Tapering for Given NN(cont(cont’’d)d) Result: every stage has equal fanout: In other words, size of each stage is geometric mean of two neighbors: Equal fanout Æ every stage will have same delay,,1,1 ,in j in jin j in jCCCC+−=EE14115EECS14115Lecture #6,1/NLinfFCC==NFf =()NpinvtNt Fγ=+Optimum Delay and Number of StagesOptimum Delay and Number of Stages When each stage has same fanout f : Effective fanout of each stage: Minimum path delay:EE14116EECS14116Lecture #6ExampleExampleCL= 8 C1InOutC11 ff 2283==fCL/C1has to be evenly distributed across N = 3 stages:EE14117EECS14117Lecture #6Delay Optimization Problem #2Delay Optimization Problem #2 You are given: The size of the first inverter The size of the load that needs to be driven Your goal: Minimize delay by finding optimal number and sizes of gates So, need to find N that minimizes:()Npinv LintNt CCγ=+EE14118EECS14118Lecture #6()()()1/lnlnNp inv L in inv L inftNtCC t CCfγγ⎛⎞+=+=⎜⎟⎝⎠()2ln 1ln 0lnpinv L intfftCCffγ∂−−=⋅=∂Forγ= 0, f = e, N = ln (CL/Cin)()ln lnLinNLinCCfCC Nf=→=()ffγ+= 1expSolving the OptimizationSolving the Optimization Rewrite N in terms of fanout/stage f:EE14119EECS14119Lecture #6Optimum Effective Fanout Optimum Effective Fanout ff()ffγ+= 1exp Optimum f for given process defined by γ0 0.5 1 1.5 2 2.5 32.533.544.55γfoptfopt= 3.6for γ = 1eEE14120EECS14120Lecture #6In Practice: Plot of Total DelayIn Practice: Plot of Total Delay Curves very flat for f > 2 Simplest/most common choice: f = 4[Hodges, p.281]EE14121EECS14121Lecture #6(),Npinv LintNt FFCCγ=+ =Normalized Delay As a Function of Normalized Delay As a Function of FFTextbook: page 210(γ = 1)EE14122EECS14122Lecture #6Buffer DesignBuffer Design111186464646442.881622.6Nf tp16465281834154 2.8 15.3EE14123EECS14123Lecture #6What About Energy (and Area)?What About Energy (and Area)?Ignoring diffusion capacitance:Ctot= Cin+ f·Cin+ … + fN·Cin= Cin·(1 + f + … + fN)= Cin+ Cin·fN+ Cin·f·(1 + f + … + fN-2)Overhead !!! f(fN-1-1) / (f-1)Example (γ=0):CL= 20pF; Ci= 50fF → N = 6Fixed: 20pFOverhead: 11.66pF !!!EE14124EECS14124Lecture #6Example Overhead NumbersExample Overhead NumbersExample: CL= 20pF; Cin= 50fF2 3 4 5 6 7 8 9 1005101520252 3 4 5 6 7 8 9 100510152025Overhead Capacitance (pF)2 3 4 5 6 7 8 9 10152025303540Delay (tinv)Number of StagesEE14125EECS14125Lecture #6Next LectureNext Lecture Gate Delay Logical
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