EE141 1 EE141 EECS141 1 Lecture #11 EE141 EECS141 2 Lecture #11 Not much new with respect to yesterday …EE141 2 EE141 EECS141 3 Lecture #11 Last lecture Technology scaling Today’s lecture CMOS logic gates Getting geared up for the project Reading (Chapter 6) EE141 EECS141 4 Lecture #11EE141 3 EE141 EECS141 5 Lecture #11 Combinational Sequential Output = f ( In ) Output = f ( In, Previous In ) EE141 EECS141 6 Lecture #11 At every point in time (except during the switching transients) each gate output is connected to either VDD or VSS via a low resistive path. The outputs of the gates assume at all times the value of the Boolean function implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit style, which relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes.EE141 4 EE141 EECS141 7 Lecture #11 VDD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks PUN and PDN functions are complementary … … EE141 EECS141 8 Lecture #11 Y = X if A AND B Y = X if A OR B Transistor ↔ switch controlled by its gate signal NMOS switch closes when switch control input is high NMOS transistors pass a “strong” 0 but a “weak” 1 A B X Y X Y A B AND OREE141 5 EE141 EECS141 9 Lecture #11 PMOS switch closes when switch control is low PMOS transistors pass a “strong” 1 but a “weak” 0 X Y A B A B X Y NOR NAND Y = X if A AND B = A + B Y = X if A OR B = AB EE141 EECS141 10 Lecture #11 VDD VDD → 0 PDN 0 → VDD CL CL PUN VDD 0 → VDD - VTn CL VDD VDD VDD → |VTp| CL S D S D VGS S S D D VGSEE141 6 EE141 EECS141 11 Lecture #11 PUN is the dual to PDN (can be shown using DeMorgan’s Theorems) Static CMOS gates are always inverting A + B = AB AB = A + B AND = NAND + INV EE141 EECS141 12 Lecture #11 PDN: G = AB ⇒ Conduction to GND PUN: F = A + B = AB ⇒ Conduction to VDD G(In1,In2,In3,…) ≡ F(In1,In2,In3,…)EE141 7 EE141 EECS141 13 Lecture #11 13 EE141 EECS141 14 Lecture #11 OUT = D + A • (B + C) D A B C D A B CEE141 8 EE141 EECS141 15 Lecture #11 EE141 EECS141 16 Lecture #11 Y = A+BCEE141 9 EE141 EECS141 17 Lecture #11 Standard Cells General purpose logic Used to synthesize RTL/HDL Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell EE141 EECS141 18 Lecture #11 signals Routing channel VDD GNDEE141 10 EE141 EECS141 19 Lecture #11 M2 No routing channels VDD GND M3 VDD GND Mirrored Cell Mirrored Cell EE141 EECS141 20 Lecture #11EE141 11 EE141 EECS141 21 Lecture #11 Cell boundary N Well Cell height 12 metal tracks Metal track is approx. 3λ + 3λ Pitch = repetitive distance between objects Cell height is “12 Mn pitch” 2λ Rails ~10λ In Out V DD GND EE141 EECS141 22 Lecture #11 In Out V DD GND In Out V DD GND With silicided diffusion With minimal diffusion routingEE141 12 EE141 EECS141 23 Lecture #11 23 A Out V DD GND B 2-input NAND gate EE141 EECS141 24 Lecture #11 24 Contains no dimensions Represents relative positions of transistors In Out V DD GND Inverter A Out V DD GND B NAND2EE141 13 EE141 EECS141 25 Lecture #11 X C A B A B C X VDD GND VDD GND EE141 EECS141 26 Lecture #11 C A B X = C • (A + B) B A C i j VDD X X i GND A B C PUN PDN A B C Logic Graph jEE141 14 EE141 EECS141 27 Lecture #11 j VDD X X i GND A B C A B C Has PDN and PUN A B C Has PUN, but no PDN EE141 EECS141 28 Lecture #11 C A B X = (A+B)•(C+D) B A D VDD X X GND A B C PUN PDN C D D A B C DEE141 15 EE141 EECS141 29 Lecture #11 EE141 EECS141 30 Lecture #11 One finger Two fingers (folded) Less diffusion capacitanceEE141 16 EE141 EECS141 31 Lecture #11 Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors EE141 EECS141 32 Lecture #11 CMOS logic -
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