1EE141 – Fall 2005Lecture 7Propagation Delay, Propagation Delay, Power DissipationPower DissipationEE141 2Important! Software Lab 3 this week Enrollments increased to 86 Hw-3 due on Thursday 5pm• Check it out early (time to ask questions)2EE141 3Today’s Lecture Inverter Performance Power DissipationReview:MOS Capacitances: MOS Capacitances: Dynamic BehaviorDynamic Behavior3EE141 5CGDCGSCSBCDBCGB(Miller)Capacitive Device Model= CGCS+ CGSO= CGCD+ CGDO= CGCB= CdiffGSDB= CdiffEE141 6Gate-Channel CapacitanceSDGCGCSDGCGCSDGCGCCut-off Resistive SaturationOff/Lin Æ Cgate= Cox·W·LeffTextbook: page 109CGCBCGCSCGCDSat Æ Cgate= (2/3)·Cox·W·LeffoxoxoxtCε=4EE141 7Gate Overlap CapacitancedoxOxCC⋅=xdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WxdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WOff/Lin/Sat Æ CGSO= CGDO= CO·Wtoxn+n+Cross sectionLGate oxidetoxn+n+Cross sectionLGate oxideEE141 8Diffusion CapacitanceBottomSide wallSide wallChannelSourceChannel-stop implantSubstrateWNA+NALSNDxjCdiff= Cbottom+ Csw= Cj· AREA + Cjsw· PERIMETEROff/Lin/Sat Æ Cdiff= Cj·LS·W + Cjsw·(2LS+W)5EE141 9Capacitive Device Model Gate-Channel Capacitance• CGC= Cox·W·Leff(Off, Linear)• CGC= (2/3)·Cox·W·Leff(Saturation) Gate Overlap Capacitance• CGSO= CGDO= CO·W (Always) Junction/Diffusion Capacitance• Cdiff= Cj·LS·W + Cjsw·(2LS+ W) (Always)Zero-bias Æ Cdiff> CgateMOS On Æ Cdiff≤ CgateEE141 10FanoutVoutVinCLSimplifiedModelM3M4M1M 2CwCg3Cdb1Cg4Vout2Cdb2VDDVDDVinVoutCgd12Computing the Capacitances123Miller effectReverse biased junctionOff Æ Sat (M4)Lin (M3)4No Miller effect6EE141 11Computing the CapacitancesMiller effect(Off Æ Sat*)(Lin*)* assuming LH transition at VoutReverse biased junction123Propagation DelayPropagation Delay7EE141 13CMOS Inverter Propagation Delay: Approach 1VoutIavgVDDVin=VDDCLavgswingLpHLIVCt2⋅=DDnLpHLVkCt⋅~EE141 14CMOS Inverter Propagation Delay: Approach 2VoutRnVDDVin=VDDCL)(LonpHLCRft⋅=LonCR⋅=69.00.360.51RonCLtVoutln(0.5)VDD8EE141 15MOS Transistor as a SwitchTraversed pathIDVDSVDDVDD /2VGS = VDDRmidR0∫∫⋅−=⋅−===212121)()(1)(1))((1212ttDDSttontttoneqdttItVttdttRtttRavgR())()(2121tRtRRononeq+⋅≈VGS≥ VTSDRonEE141 16The Transistor as a SwitchVGS≥ VTSDRon()()⋅+⋅+⋅+⋅⋅=212121DDDSATDDDDDSATDDeqVIVVIVRλλ⋅⋅−⋅≈DDDSATDDeqVIVRλ65143IDVDSVDDVDD /2VGS = VDDRmidR0()021RRRmideq+⋅=9EE141 170 0.5 1 1.5 2 2.5x 10-10-0.500.511.522.53t (sec)Vout(V)tp= 0.69 CL·(Reqn+Reqp)/2?tpHLtpLHTransient ResponseEE141 18Design for Performance Keep capacitances small Increase transistor sizes• watch out for self-loading! Increase VDD(?)10EE141 190.8 1 1.2 1.4 1.6 1.8 2 2.2 2.411.522.533.544.555.5VDD(V)tp(normalized)Delay as a function of VDD)2(')(52.04369.0DSATnTnDDDSATnnnDDLDSATnDDLpHLVVVVkLWVCIVCt−−⋅⋅⋅⋅=⋅=ReqEE141 202 4 6 8 10 12 1422.22.42.62.833.23.43.63.8x 10-11Stp(sec)Device Sizing(fixed load)Self-loading effect:Intrinsic capacitancesdominate11EE141 211 1.5 2 2.5 3 3.5 4 4.5 533.544.55x 10-11βtp(sec)NMOS/PMOS RatiotpLHtpHLtpβ = Wp/WnEE141 22tpHL(nsec)0.350.30.250.20.15trise (nsec)10.80.60.40.20Impact of Rise Time on Delaytp= tstep(i)+ η·tstep(i-1)12Power DissipationPower DissipationEE141 24Where Does Power Go in CMOS? Dynamic Power Consumption• Charging and discharging capacitors Short Circuit Currents• Short-circuit path between supply rails during switching Leakage• Leaking diodes and transistors13EE141 25#1: Dynamic Power DissipationVinVoutCLVdd Not a function of transistor sizes! Need to reduce CL, Vdd, and f to reduce powerEnergy/transition = CL·Vdd2Power = Energy/transition·f = f·CL·Vdd2EE141 26Modification for Circuits with Reduced Swing Can exploit reduced swing for lower power(e.g., reduced bit-line swing in memory)E0→1 = CL·Vdd·(Vdd– Vt)CLVddVdd –VtVdd14EE141 27Adiabatic Chargingi(t) RCCConsiderCharging a capacitor∫⋅⋅=⋅=TavgCTICdtiCV011221ddVC ⋅TVCICavg⋅=202022)(CTavgTavgdisVCTCRTIRdtIRdttiRE ⋅⋅⋅=⋅⋅=⋅≥⋅=∫∫EE141 28Adiabatic ChargingCCCIVdtdVCRVIRV +⋅=+⋅=VI= constExponential current221CRVCE ⋅=2CRVCTRCE ⋅=I = IavgLinear ramp on VIminimal energywins if T > 2RCtItItVtV15EE141 29Node Transition Activity and Power Consider switching a CMOS gate for N clock cyclesEN = CL·Vdd2·n(N)EN: the energy consumed for N clock cyclesn(N): the number of 0→1 transitions in N clock cyclesclkddLNclkNNavgfVCNNnfNEP ⋅⋅⋅=⋅=∞→∞→2)(limlimNNnN)(lim10∞→→=αPavg = α0→1·CL·Vdd2·fclkEE141 30#2: Short-Circuit CurrentsVinVoutCLVdd0.150.100.055.04.03.02.01.00.0IVDD(mA)Vin(V)16EE141 31Short circuit current goes to zero if tfall>> trise,but can’t do this for cascade logic, so ...How To Keep Short-Circuit Currents Down?EE141 320 1 2 3 4 5012345678Vdd =1.5Vdd =2.5Vdd =3.3Minimizing Short-Circuit Power Keep the input and output rise/fall times the same (<10% of total consumption) If Vdd< VTn+ |VTp| then short-circuit power can be eliminated!From: Veendrick, IEEE Journal of Solid-State Circuits, Aug’84tsin /tsoutPnorm17EE141 33Vo u tVd dSub-ThresholdCurrentDrain JunctionLeakageSub-threshold current is one of the most compelling issuesin low-energy circuit design!#3: LeakageEE141 34Np+p+Reverse Leakage Current+-VddGATEIDL = JS × AJS= 10-100 pA/µm2 at 25 deg C for 0.25µm CMOSJSdoubles for every 9 deg C!Reverse-Biased Diode Leakage18EE141 35IDversus VGS0 0.5 1 1.5 2 2.5012456x 10-4Long ChannelShort ChannelquadraticlinearquadraticVGS(V)ID(A)3EE141 36Sub-Threshold ConductionTypical values for S:60 – 100 mV/decadeThe Slope FactorS is ∆VGSfor ID2 /ID1=100 0.5 1 1.5 2 2.510-1210-1010-810-610-410-2VTLinearExponentialQuadraticVGS(V)ID(A)qkTCCneIIToxDnVDTGS=+=∝φφ,1019EE141 37Sub-Threshold Leakage Component Leakage control is critical for low-voltage operationEE141 38VDSfrom 0 to 0.5V−=−kTqVnkTqVDDSGSeeII 10Sub-Threshold IDvs. VGSIDVGS20EE141 39Sub-Threshold IDvs. VDS()DSkTqVnkTqVDVeeIIDSGS⋅+−=−λ110VGSfrom 0 to 0.3VIDVDSHw3, Prob4n=1.5kT/q = 26mVEE141 40Vin=5VVoutCLVddIstatWasted energy …Should be avoided in most cases,but could help reducing energy in others (e.g. sense amps)#4: Static Power ConsumptionPstat= P(in=1)·Vdd·Istat21EE141 41 Prime choice: Reduce voltage!• Recent years have seen an acceleration in supply voltage
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