EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 3Lecture 3CMOS InverterCMOS InverterEE1412EECS141Administrative StuffAdministrative Stuff Discussions start this week Labs start next week Everyone should have an EECS instructional account http://www-inst.eecs.berkeley.edu/~inst/newusers.html Homework #1 is due today Homework #2 due next TuesdayEE1412EE1413EECS141Class MaterialClass Material Last lecture Basic metrics for IC design Today’s lecture Finish metrics (Chapter 1) Brief introduction to CMOS inverter operation (intro to Chapter 3) CMOS manufacturing process (Chapter 2) Reading (2.1-2.2, 3.3.1-3.3.2)EE14115EECS141CMOS InverterCMOS InverterEE1413EE14116EECS141The CMOS Inverter: A First GlanceThe CMOS Inverter: A First GlanceVinVoutCLVDDEE14117EECS141CMOS InverterCMOS InverterFirstFirst--Order DC AnalysisOrder DC AnalysisVOL= 0VOH= VDDVM= f(Rn, Rp)VDDVDDVin⫽VDDVin⫽0VoutVoutRnRpEE1414EE14118EECS141Simulated Inverter VTC (Spice)Simulated Inverter VTC (Spice)0 0.5 1 1.5 2 2.500.511.522.5Vin (V)Vout(V)EE14119EECS141CMOS Inverter: DC PropertiesCMOS Inverter: DC Properties VOH= VOL= VIL= VIH= NMH= NML= VM=EE1415EE14121EECS141CMOS Inverter: Transient ResponseCMOS Inverter: Transient ResponsetpHL= f(Ron.CL)= 0.69 RonCL(a) Low-to-high (b) High-to-lowVoutVoutRnRpVDDVDDVin =VDDVin =0CLCLEE14122EECS141CMOS PropertiesCMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switchingEE1416EE14123EECS141The MOS TransistorThe MOS TransistorPolysiliconAluminumEE14124EECS141MOS Transistors MOS Transistors --Types and SymbolsTypes and SymbolsDSGDSGGSD DSGNMOSEnhancementNMOSPMOSDepletionEnhancementBNMOS withBulk ContactEE1417EE14125EECS141A Modern CMOS ProcessA Modern CMOS Processp-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2DualDual--Well Well ShallowTrenchShallowTrench--Isolated CMOS ProcessIsolated CMOS ProcessEE14126EECS141Transistor LayoutTransistor Layoutp-wellSiO2polySiO2n+Cross-Sectional ViewLayout Viewpolyp-wellEE1418EE14127EECS141The Manufacturing ProcessThe Manufacturing Processhttp://bwrc.eecs.berkeley.edu/IcBookFor a complete walk-through of the process (64 steps), check theBook web-pageEE14128EECS141oxidationopticalmaskprocessstepphotoresist coatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotoresiststepper exposuredevelopmentTypical operations in a single photolithographic cycle (from [Fullman]).PhotoPhoto--Lithographic ProcessLithographic ProcessEE1419EE14129EECS141Patterning of SiOPatterning of SiO22Si-substrateSi-substrateSi-substrate(a) Silicon base material(b) After oxidation and depositionof negative photoresist(c) Stepper exposurePhotoresistSiO2UV-lightPatternedoptical maskExposed resistSiO2Si-substrateSi-substrateSi-substrateSiO2SiO2(d) After development and etching of resist,chemical or plasma etch of SiO2(e) After etching(f) Final result after removal of resistHardened resistHardened resistChemical or plasmaetchEE14130EECS141CMOS Process at a GlanceCMOS Process at a GlanceDefine active areasEtch and fill trenchesImplant well regionsDeposit and patternpolysilicon layerImplant source and drainregions and substrate contactsCreate contact and via windowsDeposit and pattern metal layersEE14110EE14131EECS141CMOS Process WalkCMOS Process Walk--ThroughThroughp+p-epi(a) Base material: p+ substrate with optional p-epi layerp+(c) After plasma etch of insulatingtrenches using the inverse of the active area maskp+p-epiSiO23SiN4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)EE14132EECS141CMOS Process WalkCMOS Process Walk--ThroughThroughSiO2(d) After trench filling, CMPplanarization, and removal of sacrificial nitride(e) After n-well and VTpadjust implantsn(f) After p-well andVTnadjust implantspEE14111EE14133EECS141CMOS Process WalkCMOS Process Walk--ThroughThrough(g) After polysilicon depositionand etchpoly(silicon)(h) After n+ source/drain andp+source/drain implants. Thesep+n+steps also dope the polysilicon.(i) After deposition of SiO2insulator and contact hole etch.SiO2EE14134EECS141CMOS Process WalkCMOS Process Walk--ThroughThrough(j) After deposition and patterning of first Al layer.Al(k) After deposition of SiO2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.AlSiO2EE14112EE14135EECS141Advanced MetallizationAdvanced MetallizationEE14136EECS141Next LectureNext Lecture Design rules Operation of the MOS
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