EE1411EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsCircuitsCircuitsLecture 14Lecture 14EE141EECS1411Lecture #15Adders + Ratioed LogicAdders + Ratioed LogicAdministrative StuffAdministrative Stuff Remember: Any MT1 re-grading requests by Werequests by We. Project – Phase 1 Posted Due April 2 Hw 5 – due today; New homework postedEE141EECS1412Lecture #15posted.EE1412Class MaterialClass Material Last lecture Logical Effort Today’s lecture Adders ReadingEE141EECS1413Lecture #15 Chapter 11FullFull--Adder Adder -- ReviewReviewABCoutCinFulladderSumadder(kill)(kill)EE141EECS1414Lecture #15EE1413The Binary AdderThe Binary AdderEE141EECS1415Lecture #15Express Sum and Carry as a function of P, G, KExpress Sum and Carry as a function of P, G, KDefine 3 new variable which ONLY depend on A, BGenerate (G) = ABGenerate (G) = ABPropagate (P) = A ⊕BKill = ATheimagecannoBTheimagecannoEE141EECS1416Lecture #15Can also derive expressions for Sand Cobased on K and PPropagate (P) = A +BNote that we will sometimes use an alternate definition forEE1414Simplest Adder: RippleSimplest Adder: Ripple--CarryCarryA0B0A1B1A2B2A3B3Ci0C0C1C2C3Worst case delay linear with the number of bitsFA FA FA FAS0S1S2S3Ci,0Co,0(= Ci,1)Co,1Co,2Co,3t=O(N)EE141EECS1417Lecture #15Goal: Make the fastest possible carry path circuittd= O(N)tadder= (N-1)tcarry+ tsumComplementary Static CMOS Full Adder: Complementary Static CMOS Full Adder: “Direct” Implementation“Direct” ImplementationABVDDVDDCiBAABACiCiAXA BBVDDABCiCiAACiBVDDSEE141EECS1418Lecture #1528 TransistorsABACiBCoEE1415Complementary Static CMOS Full AdderComplementary Static CMOS Full AdderEE141EECS1419Lecture #1528 TransistorsInversion PropertyInversion PropertyABABSCoCiFASCoCiFAEE141EECS14110Lecture #15EE1416Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting StagesAEven cell Odd cellABABABBA3FA FA FA FAA0B0S0A1B1S1A2B2S2B3S3Ci,0Co,0Co,1Co,3Co,2EE141EECS14111Lecture #15Exploit Inversion PropertyA Better Structure: The Mirror AdderA Better Structure: The Mirror AdderVDDVDDAVDDCiABBABAABKillGenerate"1"-Propagate"0"-PropagateCiABCiCiACiBBASCoEE141EECS14112Lecture #15B24 transistorsEE1417Sizing the Mirror Adder: FanoutSizing the Mirror Adder: Fanout• Since LE of carry gate is 2, want f of 2to get EF of 4to get EF of 4• Use min. size sum gates to reduceload on carry.• Total load on carry gate is:EE141EECS14113Lecture #15gate is:Cload= CCi+ (6+6+9)Cload= 2CCiSizing the Mirror AdderSizing the Mirror AdderEE141EECS14114Lecture #15•Cload= CCi+ (6+6+9) = 2CCiÆ CCi= 21• Minimum size G and K stacks to reduce diffusion loadingEE1418Mirror Adder SummaryMirror Adder Summary•The NMOS and PMOS chains are completely symmetrical. Maximum of two series transistors in the ti tcarry-generation gate.•When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. Reduction of the diffusion capacitances is particularly important.•Carry signals are critical - transistors connected to Ciare placed closest to the output.EE141EECS14115Lecture #15pp•Only the transistors in the (propagate) carry chain have to be optimized for speed. All transistors in the sum stage can be minimal size. CarryCarry--Bypass AdderBypass AdderFA FA FA FAP0G1P0G1P2G2P3G3Co,3Co,2Co,1Co,0Ci,0Also called Carry-SkipFA FA FA FAP0G1P0G1P2G2P3G3Co,2Co,1Co,0Ci,0Co,3MultiplexerBP=PoP1P2P3EE141EECS14116Lecture #15Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.EE1419CarryCarry--Bypass Adder (cont.)Bypass Adder (cont.)SetupBit 0–3tsetupSetupBit 4–7tbypassSetupBit 8–11SetupBit 12–15CarrypropagationSumMbitstsumCarrypropagationSumCarrypropagationSumCarrypropagationSumEE141EECS14117Lecture #15M bitstadder= tsetup+ (M-1)tcarry+ (N/M-1)tbypass+ (M-1)tcarry+ tsumCarry Ripple versus Carry BypassCarry Ripple versus Carry Bypasstpripple adderbypass adderEE141EECS14118Lecture #15N4..8EE14110CarryCarry--Select AdderSelect AdderSetupP,G"0" Carry Propagation"1" Carry PropagationMultiplexerCo,k-1Co,k+3"0""1"EE141EECS14119Lecture #15Sum GenerationCarry VectorCarry Select Adder: Critical Path Carry Select Adder: Critical Path SetupBit 0–3 Bit 4–7 Bit 8–11 Bit 12–15Setup Setup Setup01Sum GenerationMultiplexer1-Carry0-CarryCi,0Co,3Co,7Co,11Co,1501Sum GenerationMultiplexer1-Carry0-Carry01Sum GenerationMultiplexer1-Carry0-Carry 0-Carry01Sum GenerationMultiplexer1-CarryEE141EECS14120Lecture #15S0–3S4–7S8–11S12–15EE14111Linear Carry Select Linear Carry Select Setup Setup Setup SetupBit 0-3 Bit 4-7 Bit 8-11 Bit 12-15(1)"0" Carry "1" Carry MultiplexerSG ti"0""1""0" Carry "1" Carry MultiplexerSG ti"0""1""0" Carry "1" Carry MultiplexerSG ti"0""1""0" Carry "1" Carry MultiplexerSG ti"0""1"Ci,0(1)(5)(6) (7) (8)(9)(5) (5) (5)(5)EE141EECS14121Lecture #15Sum GenerationSum GenerationSum GenerationSum GenerationS0-3S4-7S8-11S12-15(10)Square Root Carry Select Square Root Carry Select SetupSetup Setup SetupBit 0-1 Bit 2-4 Bit 5-8 Bit 9-13(1)Bit 14-19"0" Carry "1" Carry MultiplexerSum Generation"0""1""0" Carry "1" Carry MultiplexerSum Generation"0""1""0" Carry "1" Carry MultiplexerSum Generation"0""1""0" Carry "1" Carry MultiplexerSum Generation"0""1"Ci,0(4) (5) (6) (7)(1)(3) (4) (5) (6)MuxSum(7)(8)(3)EE141EECS14122Lecture #15S0-1S2-4S5-8S9-13S14-19(9)MEE14112Adder Delays Adder Delays -- Comparison Comparison Ripple adder4050Linear selectRipple addertp(in unit delays)10203040EE141EECS14123Lecture #15Square root select20 40N600100Logarithmic (Tree) Adders Logarithmic (Tree) Adders –– Basic IdeaBasic Idea “Look ahead” across groups of multiple bits to figure out the carryE ample ith t o bit gro psExample with two bit groups:P1:0= P1·P0, G1:0= G1+ P1·G0, Æ Cout1= G1:0+ P1:0·Cin Combine these groups in a tree structure: Delay is now ~log2(N) Instead of~NP7, G7PGP6, G6P5, G5PGPGP7:6, G7:6P7:4, G7:4EE141EECS14124Lecture #15Instead of NP4, G4P3, G3PGP2, G2P1, G1PGP0, G0PGP5:4, G5:4PGP3:2, G3:2P1:0, G1:0PGP3:0, G3:0P7:0, G7:0EE14113Rest of the TreeRest of the Tree Previous picture shows only half of the algorithmNeed to generate carries at individual bit positions tooNeed to generate carries at individual bit positions tooEE141EECS14125Lecture #15Many Kinds of Tree AddersMany Kinds of Tree Adders Many ways to construct these tree (or “carry lookahead”) addersoo a ead ) adde s Many of
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