1EE141Sequential LogicEE141- Spring 2003Lecture 22EE141Writing into a Static LatchCLKCLKCLKQDCLKCLKDConverting into a MUXForcing the state(can implement as NMOS-only)Use the clock as a decoupling signal,that distinguishes between the transparent and opaque states2EE141Cross-Coupled PairsForbidden StateSSRQQQQRSQQ00Q101001010110QNOR-based set-resetThe “Overpowering” ApproachEE141Cross-Coupled NANDSQQM1M2M3M4QM5SM6LKM7RM8CLKVDDQCross-coupled NANDsAdded clockThis is not used in datapaths any more,but is a basic building memory cell3EE141Sizing IssuesOutput voltage dependenceon transistor widthTransient response4.03.53.0W/L5 and 6(a)2.52.00.00.51.01.52.0Q (Volts)time (ns)(b)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2012W=1 mµ3VoltsQ SW=0.9 mµW=0.8 mµW=0.7 mµW=0.6 mµW=0.5 mµEE141Master-Slave (Edge-Triggered) Register10DCLKQMMaster01CLKQSlaveQMQDCLKTwo opposite latches trigger on edgeAlso called master-slave latch pair4EE141Master-Slave RegisterQMQDCLKT2I2T1I1I3T4I5T3I4I6Multiplexer-based latch pairEE141Clk-Q DelayDQCLK⫺0.50.51.52.5tc ⫺ q(lh)0.5 1 1.5 2 2.50time, nsecVoltstc ⫺ q(hl)5EE141Setup TimeDQQMCLKI2⫺ T2⫺0.5Volts0.00.2 0.4time (nsec)(a) Tsetup⫽ 0.21 nsec0.6 0.8 100.51.01.52.02.53.0DQQMCLKI2⫺ T2⫺0.5Volts0.00.2 0.4time (nsec)(b) Tsetup⫽ 0.20 nsec0.6 0.8 100.51.01.52.02.53.0EE141Reduced Clock LoadMaster-Slave RegisterDQT1I1CLKCLKT2CLKCLKI2I3I46EE141Avoiding Clock OverlapCLKCLKAB(a) Schematic diagram(b) Overlapping clock pairsXDQCLKCLKCLKCLKEE141More Precise Setup TimetD ⫺ CttttC ⫺ Q1.05tC ⫺ QtSutHClkDQ(b)(a)7EE141Clk-Q DelayTSetup-1TClk-QTimeSetup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)DCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1EE141Clk-Q DelayTSetup-1TClk-QTimeTimet=0ClockDataTSetup-1Setup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)DCNQMCPD1SMInv1Inv2TG18EE141Clk-Q DelayTSetup-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1Setup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)EE141Clk-Q DelayTSetup-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1Setup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)9EE141Timet=0ClockDataTSetup-1DCNQMCPD1SMInv1Inv2TG1Setup-Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)Clk-Q DelayTSetup-1TClk-QTimeEE141Setup-Hold Time IllustrationsHold-1 caseDCNQMCPD1SMInv1Inv2TG1Timet=0DataClockTHold-10Clk-Q DelayTHold-1TClk-QTime10EE141Clk-Q DelayTHold-1TClk-QTimeTimet=0DataClockTHold-1Setup-Hold Time IllustrationsHold-1 caseDCNQMCPD1SMInv1Inv2TG10EE141Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0DataClockTHold-1Setup-Hold Time IllustrationsHold-1 case011EE141Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockTHold-1DataSetup-Hold Time IllustrationsHold-1 case0EE141Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockTHold-1DataSetup-Hold Time IllustrationsHold-1 case0⇒12EE141Other Latches/Registers: C2MOSM1DQM3CLKM4M2CLKVDDCL1XCL2Master StageM5M7CLKCLKM8M6VDDSlave StageKeepers can be added to staticizeEE141Other Latches/Registers: TSPCCLKnVDDCLKVDDInOutCLKVDDCLKVDDOutNegative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)13EE141Including Logic in TSPCCLKn CLKVDDVDDQPUNPDNCLKVDDQCLKVDDIn1In1In2In2AND latchExample: logic inside the latchEE141TSPC RegisterCLKCLKDVDDM3M2M1CLKYVDDQQM9M8M7CLKXVDDM6M5M414EE141Pulse-Triggered LatchesMaster-SlaveLatchesDClkQ DClkQClkDataDClkQClkDataPulse-TriggeredLatchL1 L2 LWays to design an edge-triggered sequential cell:EE141Pulsed LatchesCLKGDVDDM3M2M1CLKGVDDM6QM5M4CLKCLKGVDDXMPMN(a) register (b) glitch generationCLKCLKG(c) glitch clock15EE141Pulsed LatchesHybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :P1M3M2DCLKM1P3M6QxM5M4P2CLKDEE141HLFF Timing20.50.00.51.01.52.02.53.00.20.0 0.4QDtime (ns)Volts0.6 0.8 1.0CLKDCLK16EE141PipeliningREGREGREGlogCLKCLKCLKOutREGREGREGlogCLKCLKCLKREGCLKREGCLKOutReferencePipelinedEE141Latch-Based PipelineF GCLKCLKn OutC1C2CLKC3CLKCLKCompute F compute G17EE141Other Sequential CircuitsSchmitt TriggerMonostable MultivibratorsAstable MultivibratorsEE141Schmitt TriggerIn OutVinVoutVOHVOLVM–VM+•VTC with hysteresis•Restores signal slopes18EE141Noise Suppression usingSchmitt TriggerVint0M−M+tVoutt0+tptEE141CMOS Schmitt TriggerMoves switching thresholdof the first inverterVinM2M1VDDXVoutM4M319EE141Schmitt TriggerSimulated VTC2.5VX(V)VM2VM1Vin(V)Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4. The width is k* 0.5 m.2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.52.5Vx(V)k=2k=3k=4k=1Vin(V)2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.5EE141CMOS Schmitt Trigger (2)VDDVDDOutnM1M5M2XM3M4M620EE141Multivibrator CircuitsBistable MultivibratorMonostable MultivibratorAstable Multivibratorflip-flop, Schmitt Triggerone-shotoscillatorSRTEE141Transition-Triggered MonostableDELAYtdInOuttd21EE141Monostable Trigger (RC-based)VDDInOutABCRInBOuttVMt2t1(a) Trigger circuit.(b) Waveforms.EE141Astable Multivibrators (Oscillators)012 N-1Ring Oscillatorsimulated response of 5-stage oscillator0.00.00.51.01.52.02.5V1V3V53.020.50.5time (ns)Volts1.0 1.522EE141Relaxation OscillatorOut2CROut1IntI1I2T = 2 (log3) RCEE141Voltage Controller Oscillator (VCO)InVDDM3M1M2M4M5VDDM6VcontrCurrent starved inverterIrefIrefSchmitt Triggerrestores signal slopes0.5 1.5 2.5Vcontr(V)0.0246tpHL(nsec)propagation delay as a functionof control
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