1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on March 10, 2002 by Jason Hu ([email protected]) Jan M. Rabaey Homework #7: EECS 141 Andrei Vladimirescu Due 3/22/02 at 5pm, 558 Cory Problem #1: Pass Transmission Gate The figure below is a logic gate that also incorporates a transmission gate in between the output node F and input node B. a) Determine the logic function of this gate. (F = …) b) We would like to implement this gate using one stage of dynamic logic instead of pass transistors. There are two possible implementations that result in the same logic output. Give the dynamic logic implementation using an NMOS pull-down network and the implementation using a PMOS pull-up network. Assume that you have complementary inputs. Problem #2: Sizing of Static Logic Gates You are given the above combinational logic network implemented in simple complementary CMOS logic. The first gate is a minimum sized 2-input symmetrical NAND gate (this is, the NMOS transistors have been sized up to compensate for the series devices). C is the input capacitance of a minimum-sized inverter. 20C20C20C12 Determine the sizing factors y and z (for the 2nd and 3rd stage, respectively) that minimize the delay between nodes A and B. Problem #3: Dynamic Gates For this problem, please assume the following: The bulk of your transistors are tied to their respective supplies Cdb,p = Csb,p = Cdb,n = Csb,n = 8.0fF Cgd,p = Cgd,n = 12.0fF Vt,p = 0.7V – when body effect is present Vdd = 2.5V You’ve just been hired on at Ligence, one of Intel’s competitors. You may be just starting off, but since you’re omnipotent at this digital circuit stuff, your design for Ligence’s new flagship chip, the 10.0GHz JAMmer chip is done, more than 6 months ahead of schedule! Your manager looks to you and says, “Oh great (Place name here), please help me decipher this logic gate in the chip you so ingeniously designed.” Your circuit is shown below in Figure 1a. X Y Figure 1a – Your ingenious logic block3 The two of you pull up some chairs and start reviewing the design. Your manager turns to you and asks you the following questions: a) What is the logic function of the above circuit? b) Given the following inputs, shown in Figure 1b, please trace out the waveforms at the following nodes: X, Y, and OUT. Assume that these nodes are initially at ground. Approximate the timing, but be accurate when indicating the voltage levels for the waveforms. Be sure to show your work. (hint: think about charge sharing) Figure 1b – Input Waveforms c) I want to cascode your dynamic block with the corresponding pull-down network , using OUT1 as the input A for the next stage. Give the schematic of such a block. d) For the schematic in part c, what is the maximum voltage obtainable at its output (OUT2)? Assume that the pull-down network has a 70.0fF load at its
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