EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 4Lecture 4CMOS Manufacturing ProcessCMOS Manufacturing ProcessDesign RulesDesign RulesEE1412EECS141Administrative StuffAdministrative Stuff Discussions start this week Labs start next week Everyone should have an EECS instructional account http://www-inst.eecs.berkeley.edu/~inst/newusers.html All lab sessions are on Homework #2 due next TuesdayEE1412EE1413EECS141Class MaterialClass Material Last lecture Brief introduction to CMOS inverter operation Today’s lecture CMOS manufacturing process (Ch. 2.1-2.2) Design rules (Ch. 2.3) Reading (2.1-2.2, 3.3.1-3.3.2)EE1414EECS141The MOS TransistorThe MOS TransistorPolysiliconAluminumEE1413EE1415EECS141A Modern CMOS ProcessA Modern CMOS Processp-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2DualDual--Well ShallowWell Shallow--TrenchTrench--Isolated CMOS ProcessIsolated CMOS ProcessEE1416EECS141Transistor LayoutTransistor Layoutp-wellSiO2polySiO2n+Cross-Sectional ViewLayout Viewpolyp-wellEE1414EE1417EECS141The Manufacturing ProcessThe Manufacturing Processhttp://bwrc.eecs.berkeley.edu/IcBookFor a complete walk-through of the process (64 steps), check theBook web-pageEE1418EECS141oxidationopticalmaskprocessstepphotoresist coatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotoresiststepper exposuredevelopmentTypical operations in a single photolithographic cycle (from [Fullman]).PhotoPhoto--Lithographic ProcessLithographic ProcessEE1415EE1419EECS141Patterning of SiOPatterning of SiO22Si-substrateSi-substrateSi-substrate(a) Silicon base material(b) After oxidation and depositionof negative photoresist(c) Stepper exposurePhotoresistSiO2UV-lightPatternedoptical maskExposed resistSiO2Si-substrateSi-substrateSi-substrateSiO2SiO2(d) After development and etching of resist,chemical or plasma etch of SiO2(e) After etching(f) Final result after removal of resistHardened resistHardened resistChemical or plasmaetchEE14110EECS141CMOS Process at a GlanceCMOS Process at a GlanceDefine active areasEtch and fill trenchesImplant well regionsDeposit and patternpolysilicon layerImplant source and drainregions and substrate contactsCreate contact and via windowsDeposit and pattern metal layersEE1416EE14111EECS141CMOS Process WalkCMOS Process Walk--ThroughThroughp+p-epi(a) Base material: p+ substrate with optional p-epi layerp+(c) After plasma etch of insulatingtrenches using the inverse of the active area maskp+p-epiSiO23SiN4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)EE14112EECS141CMOS Process WalkCMOS Process Walk--ThroughThroughSiO2(d) After trench filling, CMPplanarization, and removal of sacrificial nitride(e) After n-well and VTpadjust implantsn(f) After p-well andVTnadjust implantspEE1417EE14113EECS141CMOS Process WalkCMOS Process Walk--ThroughThrough(g) After polysilicon depositionand etchpoly(silicon)(h) After n+ source/drain andp+source/drain implants. Thesep+n+steps also dope the polysilicon.(i) After deposition of SiO2insulator and contact hole etch.SiO2EE14114EECS141CMOS Process WalkCMOS Process Walk--ThroughThrough(j) After deposition and patterning of first Al layer.Al(k) After deposition of SiO2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.AlSiO2EE1418EE14115EECS141Advanced MetallizationAdvanced MetallizationEE14116EECS141Design RulesDesign Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)EE1419EE14117EECS141Design RulesDesign Rules Intra-layer Widths, spacing, area Inter-layer Enclosures, distances, extensions, overlaps Special rules (sub-0.25µm) Antenna rules, density rules, (area)EE14118EECS141CMOS Process LayersCMOS Process LayersLayerPolysiliconMetal1Metal2Contact To PolyContact To DiffusionViaWell (p,n)Active Area (n+,p+)Color RepresentationYellowGreenRedBlueMagentaBlackBlackBlackSelect (p+,n+)GreenEE14110EE14119EECS141Layers in 0.25 Layers in 0.25 μμm CMOS processm CMOS processEE14120EECS141IntraIntra--Layer Design RulesLayer Design RulesMetal2431090 WellActive33Polysilicon22Different PotentialSame PotentialMetal1332Contactor ViaSelect2or62HoleEE14111EE14121EECS141Transistor LayoutTransistor Layout1253TransistorEE14122EECS141ViasViasand Contactsand Contacts121ViaMetal toPoly ContactMetal toActive Contact1254322EE14112EE14123EECS141EE14124EECS141Select LayerSelect Layer133222WellSubstrateSelect35EE14113EE14125EECS141CMOS Inverter LayoutCMOS Inverter LayoutAA’np-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-A’AA’EE14126EECS141Layout EditorLayout EditorEE14114EE14127EECS141Design Rule CheckerDesign Rule CheckerEE14128EECS141Sticks DiagramSticks Diagram13InOutVDDGNDStick diagram of inverter• Dimensionless layout entities• Only topology is importantEE14115EE14129EECS141Circuit Under DesignCircuit Under DesignVDDVDDVinVoutM1M2M3M4Vout2EE14130EECS141CMOS InverterCMOS InverterPolysiliconInOutVDDGNDPMOS2λMetal 1NMOSOutInVDDPMOSNMOSContactsN WellEE14116EE14131EECS141Two InvertersTwo InvertersConnect in MetalShare power and groundAbut cellsVDDEE14132EECS141Next LectureNext Lecture Operation and modeling of the MOS
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