EE141EE141EECS1411Lecture #18EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsLectureLecture1818Domino LogicDomino LogicPower RevisitedPower RevisitedEE141EECS1412Lecture #18AnnouncementsAnnouncements Project Phase 1 due Today! Midterm 2 next We – 6:30-8pm 105 North Gate Covers all material up to (and including) dynamic logic Review session next TuEE141EE141EECS1413Lecture #18Class MaterialClass Material Last lecture Dynamic Logic Today’s lecture Domino logic Revisit power Reading Chapter 6, Chapter 7EE141EECS1414Lecture #18Dynamic Dynamic Gate Gate --RevisitedRevisitedIn1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMeTwo phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)onoff1offon((AB)+C)EE141EE141EECS1415Lecture #18Issues in Dynamic LogicIssues in Dynamic Logic Charge Leakage Charge redistribution Clock feedthrough Back-gate coupling Cascading of gatesEE141EECS1416Lecture #18Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge SharingCLClkClkCACBB=0AOutMpMe Charge initially stored on CL CApreviously discharged When A rises, this charge is redistributed (shared) between CLand CA Makes Out drop below VDDEE141EE141EECS1417Lecture #18Charge Sharing ExampleCharge Sharing ExampleEE141EECS1418Lecture #18Charge SharingCharge SharingB=0ClkXCLCaCbAOutMpMaVDDMbClkMe• Two cases:•Mastays on – complete charge share•Maturns off – incomplete charge share•Complete charge share:•QCa= VOutCaΔQCL= -VOutCaÆ ΔVOut= -VDDCa/(Ca+CL)•Incomplete charge share:•QCa= (VDD-VTN*)CaΔQCL= -(VDD-VTN*)CaÆ ΔVOut= -(VDD-VTN*)Ca/CLEE141EE141EECS1419Lecture #18Solution to Charge SharingSolution to Charge SharingClkClkMeMpABOutMkpClk• Keeper helps a lot• Can still get failures if Out drops below inverter Vsw• Another option: precharge internal nodes• Increases power and areaEE141EECS14110Lecture #18Issues in Dynamic Design 3: Clock Issues in Dynamic Design 3: Clock FeedthroughFeedthroughCLClkClkBAOutMpMeCoupling between Out and Clk input of the prechargedevice due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.EE141EE141EECS14111Lecture #18Clock FeedthroughClock Feedthrough-0.50.51.52.500.51ClkClkIn1In2In3In4OutIn &ClkOutTime, nsVoltageClock feedthroughClock feedthroughEE141EECS14112Lecture #18Issues in Dynamic Design 4: Issues in Dynamic Design 4: BackgateBackgateCouplingCouplingCL1ClkClkB=0A=0Out1MpMeOut2CL2InDynamic NAND Static NAND=1=0EE141EE141EECS14113Lecture #18BackgateBackgateCoupling EffectCoupling Effect-101230246VoltageTime, nsClkInOut1Out2EE141EECS14114Lecture #18Other EffectsOther Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) Cascading dynamic gatesEE141EE141EECS14115Lecture #18Cascading Dynamic GatesCascading Dynamic GatesClkClkOut1InMpMeMpMeClkClkOut2VtClkInOut1Out2ΔVVTnOnly 0 → 1 transitions allowed at inputs!EE141EECS14116Lecture #18Domino LogicDomino LogicEE141EE141EECS14117Lecture #18Domino LogicDomino LogicIn1In2PDNIn3MeMpClkClkOut1In4PDNIn5MeMpClkClkOut2Mkp1 → 11 → 00 → 00 → 1EE141EECS14118Lecture #18Why Named Domino?Why Named Domino?ClkClkIniPDNInjIniInjPDNIniPDNInjIniPDNInjLike falling dominos!EE141EE141EECS14119Lecture #18Properties of Domino LogicProperties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition critical Input capacitance reduced – smaller logical effortEE141EECS14120Lecture #18Domino Logic LEDomino Logic LEEE141EE141EECS14121Lecture #18Domino Logic LE (skewed static gate)Domino Logic LE (skewed static gate)EE141EECS14122Lecture #18Buffer Buffer ““AverageAverage””LELEEE141EE141EECS14123Lecture #18Designing with Domino LogicMpMeVDDPDNClkIn1In2In3Out1ClkMpMeVDDPDNClkIn4ClkOut2MrVDDInputs = 0during prechargeCan be eliminatedEE141EECS14124Lecture #18Footless DominoFootless DominoThe first gate in the chain needs a foot switchPrecharge is rippling – short-circuit currentVDDClk MpOut1In11 0VDDClk MpOut2In2VDDClk MpOutnInnIn31 00 1 0 1 0 11 0 1 0EE141EE141EECS14125Lecture #18Footless DominoFootless DominoCan mitigate short-circuit current by alternating between footed and unfooted dominoEE141EECS14126Lecture #18Footless DominoFootless DominoTo eliminate the short-circuit current, can delay the clock for each stageVDDClk MpOut1In11 0VDDClk MpOut2In2VDDClk MpOutnInnIn31 00 1 0 1 0 11 0 1 0EE141EE141EECS14127Lecture #18Differential (Dual Rail) DominoDifferential (Dual Rail) DominoABMeMpClkClkOut = AB!A !BMkpClkOut = ABMkpMpAllows inverting gates to be builtEE141EECS14128Lecture #18npnp--CMOSCMOSIn1In2PDNIn3MeMpClkClkOut1In4PUNIn5MeMpClkClkOut2(to PDN)1 → 11 → 00 → 00 → 1Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUNEE141EE141EECS14129Lecture #18NORA LogicNORA LogicIn1In2PDNIn3MeMpClkClkOut1In4PUNIn5MeMpClkClkOut2(to PDN)1 → 11 → 00 → 00 → 1Fast, but EXTREMELY sensitive to noise!EE141EECS14130Lecture #18Power Power RevisitedRevisitedEE141EE141EECS14131Lecture #18Transition Activity and PowerTransition Activity and Power Energy consumed in N cycles, EN:EN= CL• VDD2• n0→1n0→1 – number of 0→1 transitions in N cyclesfVCNnfNEPDDLNNNavg⋅⋅⋅⎟⎠⎞⎜⎝⎛=⋅=→∞→∞→210limlimfNnN⋅=→∞→→1010limαfVCPDDLavg⋅⋅⋅=→210αEE141EECS14132Lecture #18“Dynamic” or timing dependent component ÅType of Logic Function (NOR vs. XOR)“Static” component (does not account for timing)ÅCircuit TopologyÅType of Logic Style (Static vs. Dynamic)ÅSignal StatisticsÅInter-signal Co rrelationsÅSignal Statistics and CorrelationsFactors Affecting Transition ActivityFactors Affecting Transition ActivityEE141EE141EECS14133Lecture #18Type of Logic Function: NORType of Logic Function: NORABOut00 101 010 011 0Example: Static 2-input NOR GateAssume signal probabilitiespA=1 = 1/2pB=1 = 1/2Then transition probabilityp0→1 = pOut=0 x pOut=1= 3/4 x 1/4 = 3/16α0→1= 3/16If inputs switch every cycleEE141EECS14134Lecture #18Type of Logic Function: NANDType of Logic Function: NANDABOut00 101 110 111 0Example: Static 2-input NAND GateAssume signal probabilitiespA=1 = 1/2pB=1 = 1/2Then transition probabilityp0→1 = pOut=0 x
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