EECS 141: SPRING 03—FINAL 1University of CaliforniaCollege of EngineeringDepartment of Electrical Engineeringand Computer ScienceJan M. Rabaey TuTh 9:30-11amEECS 141: SPRING 03—FINALNAME LastFirstSIDTotal (75)Problem 2 (15):Problem 1 (10):Problem 3 (14):Problem 4 (18):For all problems, you can assume the following transistor parameters NMOS: VTn = 0.4V, kn’ = 115µA/V2, VDSAT = 0.6V, λ = 0, γ = 0.4V1/2, 2ΦF = -0.6VPMOS: VTp = -0.4V, kp’ = -30µA/V2, VDSAT = -1V, λ = 0, γ = -0.4V1/2, 2ΦF = 0.6V(unless otherwise mentioned):Problem 5 (18):EECS 141: SPRING 03—FINAL 2Problem 1: Timing and Clocking (10 pts)In order to boost profits, Intel has decided that their next-generation microprocessorhas to have ultimate performance. To achieve the desired performance, 16 processors areintegrated on the same die (the chip is hence called seidecium – for obvious reasons). Thedesigner of the clocking architecture has come up with the strategy shown in the Figurebelow. A single clock signal is distributed over the complete chip. Three levels of buffer-ing are used as shown by the black boxes in the Figure.a) Determine the maximum skew between the different processor modules. (4 pts)P1P16P2105131FIG. 1 Seidecium processor clock distribution network. The numbers annotated on the figure indicate the lengths of the wiring segments (in cm).Important parameters:tpbuffer (level 1,2,3) = 0.1nsrwire 0.1 kΩ()cm()⁄=cwire 0.1 pF()cm()⁄=max skew:EECS 141: SPRING 03—FINAL 3b) The goal of the designers is to reach a 4 GHz clock speed. Determine the maxi-mum delay of the logical function blocks given that 20% of the clock period is dueto the delay of registers. Also, note that the maximum internal skew within a pro-cessor module equals 20 ps. (3 pts)c) The Intel designers forgot to account for one thing though. Due to the parametersvariations over the die, it is observed that the delay of the clock buffers can varyover 25% (in both positive and negative directions). Determine the worst-caseclock speed due to these variations. (3 pts)tlogic(max)=fclock(min)=EECS 141: SPRING 03—FINAL 4Problem 2: Interconnect (15 pts)a) A driver-receiver pair in CMOS technology is shown in Figure 2. FIG. 2 Driver and receiver. Numbers on transistors indicate (W/L) ratios. Assume that all transistors are short-channel devices. VM of the driver inverter equalsVDD/2. Draw the voltage transfer characteristic VOUT versus VIN when the driver isdirectly attached to the receiver. Write down circuit analysis equations and calculatethe break points on the VTC. (4 pts) Driver Receiver VDD VDD VIN VOUT 10/2 4/2 10/2 4/2 4/10 VDD = 2.5VEECS 141: SPRING 03—FINAL 5b) The driver and receiver in a) can be used to drive intermediate circuits. Brieflycomment on the advantage and disadvantages of this driving scheme from the per-spectives of performance and power. (3 pts) c) Derive a global expression of the typical gate (being an inverter) delay in thepresence of wiring with a length equal to Lnet followed by a fanout of 4 equivalentgates. Make sure to include all components of delay. You may assume that thefollowing parameters are given: Cgate and Ron of driver (per unit width), rint andcint of interconnect (per unit length). You may assume that the diffusion capaci-tance at the output of the gate is approximately equal to its gate capacitance.Clearly state all other assumptions you are making (e.g. wire model). Thisquestion is not related to parts a) and b). (4 pts)EECS 141: SPRING 03—FINAL 6d) Discuss how you would reduce the delay if the capacitive load of the fanout is thedominant factor and discuss the minimum value of the delay. (2 pts)e) Discuss how you would reduce the delay if the interconnect delay is the dominantfactor. Derive an expression for the minimum delay. (2 pts)EECS 141: SPRING 03—FINAL 7Problem 3: Memory (14 pts)The Figure below shows a novel 2T-DRAM cell to be used in a low-voltage applica-tion. The supply voltage is fixed at 1 V. WBL is the write bit-line, RBL is the read bit-line, WL the word-line. Assume initially that node P is fixed at GND.a) Determine the signal levels (VDD or GND) that have to be applied to the controlsignals (WS, RS) to perform a write operation into and a read operation from thecell? (4 pts)b) Explain why this scheme has some major problems. (2 pts)VDDM3XClkM2M1WSPRSCbRBLWBLFIG. 3 A 2-T DRAM cell.WS (Wr):RS (Wr):WS (Rd):RS (Rd):EECS 141: SPRING 03—FINAL 8c) Instead of node P being fixed at GND, we apply a waveform as shown in figurebelow. Fill in the timing diagrams for the write operation. Denote the voltage lev-els in terms of VDD and VT. Assume there is enough time to let the transienteffects settle out (no need to draw them). Explain why this approach is substan-tially better. (6 pts)d) Does the memory cell require refresh? Why or why not? (2 pts)WBLWSPXVDD0VDDVOLVDD0WBLWSPX00VDDVOHVDD0This aproach is better because:EECS 141: SPRING 03—FINAL 9Problem 4: Multivibrator Circuits (18 pts)a) Shown in the Figure below is a design of a Schmitt trigger. Determine the (W/L)ratio of transistor M1 so that VM+=3VTn. VDD = 2.5V. You may ignore the bodyeffect in this question. You may also assume a long channel device. Clearly stateyour other assumptions. (6 pts)VinVoutVDDVDD102.5?1M1FIG. 4 Schmitt trigger. Numbers on tran-sistors indicate (W/L) ratios.(W/L)1=EECS 141: SPRING 03—FINAL 10b) Determine approximately the value of VM- (4 pts)c) Figure 5 shows an astable multivibrator. Calculate and draw voltage waveforms(see next page) at the capacitor VC and at the output Vout. (6 pts)VM-=FIG. 5 Astable multivibrator.Assumptions: Ideal amplifier with symmetric supply(Voutmax = Vcc, Voutmin = -Vcc), , C = 1 nF, Vcc = 5V, VD = 0.6V (ideal diode)Vout (t = 0-) = -VccR11kΩ= R23kΩ= R3R44kΩ==CR3R4R2R1D1D2VoutVCEECS 141: SPRING 03—FINAL 11d) What is the oscillation frequency of the multivibrator in Fig. 5? (2pts)Vout [V]0t [µs]VC [V]0t [µs]fOSC=EECS 141: SPRING 03—FINAL 12Problem 5: Scaling and Overall Knowledge (18 pts)a) Determine the region of operation (Cut off, Linear, Saturation, Vel. saturation) inthe following configurations. You may assume that all transistors are short-channeldevices and have identical sizes. Ignore body effect. VDD = 2.5V. Explain your reasoning, and show your derivations if needed (5 pts).GND GND VDD M1VDD GND VDD GND M2M3VDD GND VDD VDD M4M5EECS 141: SPRING 03—FINAL 13b) The first row of the table
View Full Document
Unlocking...