EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 5Lecture 5MOS TransistorMOS TransistorEE1412EECS141AnnouncementsAnnouncements Lab 2 this week! Lab 3 next week Homework #2 is due today Homework #3 due next TuesdayEE1412EE1413EECS141Class MaterialClass Material Last lecture CMOS manufacturing process Design rules Today’s lecture MOS transistor operation and modeling Reading (3.3.1-3.3.2)EE1414EECS141MOS TransistorMOS TransistorEE1413EE1415EECS141What is a Transistor?What is a Transistor?|VGS|A MOS Transistor|VGS| ≥ |VT|SDRonA Switch!SDGEE1416EECS141Switch Model of MOS TransistorSwitch Model of MOS Transistor|VGS|SDG|VGS| < |VT||VGS| > |VT|RonSDSDEE1414EE1417EECS141NMOS and PMOSNMOS and PMOSVGS> 0SDGVGS< 0SDGNMOS Transistor PMOS TransistorEE1418EECS141SDGBSDGSDGSDGNMOS Enhancement NMOS DepletionPMOS EnhancementNMOS withBulk ContactMOS Transistors: Types and SymbolsMOS Transistors: Types and SymbolsEE1415EE1419EECS141n+p-substrateDSGBVGS+–Depletionregionn-c hanne ln+Threshold Voltage: ConceptThreshold Voltage: ConceptEE14110EECS141The Threshold VoltageThe Threshold Voltage()FSBFTTVVV φ−+φ⋅γ+= 220iATFnNln⋅φ=φ Threshold Fermi potential2ΦFis approximately −0.6V for p-type substratesγ is the body factorVT0is approximately 0.45V for our processEE1416EE14111EECS141The Body EffectThe Body Effect-2.5 -2 -1.5 -1 -0.5 00.40.450.50.550.60.650.70.750.80.850.9VBS (V)VT (V)VT0reverse body biasEE14112EECS141n+n+p-substrateDSGBVGSxLV(x)+–VDSIDTransistor in Linear ModeTransistor in Linear ModeVGS> VDS+ VTEE1417EE14113EECS141The Drain CurrentThe Drain Current[]TGSoxiVxVVCxQ−−⋅−= )()(oxoxoxtCε= Charge in the channel is controlled by the gate voltage: Drain current is proportional to charge and velocity:WxQxIinD⋅⋅υ−= )()(dxdVxxnnn⋅μ=ξ⋅μ−=υ )()(EE14114EECS141The Drain CurrentThe Drain Current()dVVVVWCdxITGSoxnD⋅−−⋅⋅⋅μ=⋅ Combining velocity and charge: Integrating over the channel:()⎥⎥⎦⎤⎢⎢⎣⎡−⋅−⋅⋅=22DSDSTGSnDVVVVLWkI’Transconductance:oxoxnoxnntCkε⋅μ=⋅μ=’EE1418EE14115EECS141n+n+SGVGSDVDS > VGS - VTVGS - VT+-Transistor in SaturationTransistor in SaturationPinch-offVT< VGS< VDS+ VTEE14116EECS141SaturationSaturation For VGD< VT, the drain current saturates:()22TGSnDVVLWkI −⋅⋅=’ Including channel-length modulation:()( )DSTGSnDVVVLWkI ⋅λ+⋅−⋅⋅= 122’CLMEE1419EE14117EECS141Modes of OperationModes of OperationCutoff:VGS< VTResistive (Linear):VGS> VDS+VTSaturation:VT< VGS< VDS+ VT ()⎥⎥⎦⎤⎢⎢⎣⎡−⋅−⋅⋅=22DSDSTGSnDVVVVLWkI’()22TGSnDVVLWkI −⋅⋅=’0=DIEE14118EECS141QuadraticRelationship0 0.5 1 1.5 2 2.50123456x 10-4VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistive SaturationVDS= VGS-VTCurrentCurrent--Voltage Relations:Voltage Relations:A Good OlA Good Ol’’TransistorTransistorVDS(V)ID(A)EE14110EE14119EECS141A Model for Manual AnalysisA Model for Manual AnalysisSDGID()⎥⎥⎦⎤⎢⎢⎣⎡−⋅−⋅⋅=22DSDSTGSnDVVVVLWkI’()( )DSTGSnDVVVLWkI ⋅λ+⋅−⋅⋅= 122’()FSBFTTVVV φ−+φ⋅γ+= 220VDS> VGS– VTVDS< VGS– VTwithResistive:Saturation:EE14120EECS141LinearRelationship-40 0.5 1 1.5 2 2.500.511.522.5x 10VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VEarlySaturationCurrentCurrent--Voltage Relations:Voltage Relations:The Deep SubThe Deep Sub--Micron TransistorMicron TransistorVDS(V)ID(A)EE14111EE14121EECS141Velocity SaturationVelocity Saturationξ(V/µm)ξc= 1.5υn(m/s)υsat= 105Constant mobility (slope = µ)Constant velocity Velocity saturates due to carrier scattering effectsEE14122EECS141Velocity SaturationVelocity SaturationIDLong-channel deviceShort-channel deviceVDSVDSATVGS-VTVGS = VDDEE14112EE14123EECS141IIDDversus Vversus VGSGS0 0.5 1 1.5 2 2.50123456x 10-4VGS(V)ID(A)0 0.5 1 1.5 2 2.500.511.522.5x 10-4VGS(V)ID(A)quadraticquadraticlinearLong Channel(L=2.5μm)Short Channel(L=0.25μm)EE14124EECS141Regions of OperationRegions of Operation-40 0.5 1 1.5 2 2.500.511.522.5x 10VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 V0 0.5 1 1.5 2 2.50123456x 10-4VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistive SaturationVDS= VGS-VTVDS(V) VDS(V)ID(A)ID(A)ResistiveVelocitySaturationLong Channel(L=2.5μm)Short Channel(L=0.25μm)W/L=1.5EE14113EE14125EECS141Including Velocity SaturationIncluding Velocity SaturationApproximate velocity:And integrate current again:In deep submicron, there are four regions of operation:(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturationEE14126EECS141-40 0.5 1 1.5 2 2.500.511.522.5x 10VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 V0 0.5 1 1.5 2 2.50123456x 10-4VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistive SaturationVDS= VGS-VTVDS(V) VDS(V)ID(A)ID(A)Long Channel(L=2.5μm)Short Channel(L=0.25μm)Early SaturationW/L=1.5Regions of OperationRegions of OperationEE14114EE14127EECS141Regions of Operation Regions of Operation ––SimplifiedSimplifiedLinearRelationship-40 0.5 1 1.5 2 2.500.511.522.5x 10VelocitySaturationVDS(V)ID(A)VDS= VGTVDSAT= VGTSaturationLinearVDS= VDSAT Define VGT= VGS–VTVDSAT≈ L·ξcEE14128EECS141A Unified Model for Manual AnalysisA Unified Model for Manual AnalysisBDGIDS()DSGTDVVVVLWkI ⋅λ+⋅⎟⎟⎠⎞⎜⎜⎝⎛−⋅⋅⋅= 12'2minminfor VGT≤ 0: ID=0with Vmin= min (VGT, VDS, VDSAT)for VGT≥ 0:define VGT= VGS– VTEE14115EE14129EECS141Simple Model versus SPICE Simple Model versus SPICE 0 0.5 1 1.5 2 2.500.511.522.5x 10-4VDS(V)ID(A)VelocitySaturatedLinearSaturatedVDSAT=VGTVDS=VDSATVDS=VGTEE14130EECS141Transistor Model for Manual AnalysisTransistor Model for Manual AnalysisTextbook: page 103EE14116EE14131EECS141A PMOS TransistorA PMOS Transistor-2.5 -2 -1.5 -1 -0.5 0-1-0.8-0.6-0.4-0.20x 10-4VDS(V)ID(A)Assume all variablesnegative!VGS = -1.0VVGS = -1.5VVGS = -2.0VVGS = -2.5VEE14132EECS141Next LectureNext Lecture Using the MOS model: Inverter VTC and
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