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Berkeley ELENG 141 - Lecture25 - Interconnect

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EE141 1 EE141 EECS141 1 Lecture #25 EE141 EECS141 2 Lecture #25  Hw 8 due Monday May 5  Think project!EE141 2 EE141 EECS141 3 Lecture #25  Last Lecture: Resistance/Inductance  This Lecture: Interconnect Design  Next Lecture: Clock and Power Distribution EE141 EECS141 4 Lecture #25EE141 3 EE141 EECS141 5 Lecture #25 The Wave Equation EE141 EECS141 6 Lecture #25EE141 4 EE141 EECS141 7 Lecture #25 EE141 EECS141 8 Lecture #25EE141 5 EE141 EECS141 9 Lecture #25 EE141 EECS141 10 Lecture #25  Transmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight). tr (tf) << 2.5 tflight  Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z0  The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z0/2EE141 6 EE141 EECS141 11 Lecture #25 (1990, Bakoglu) 100-200ps today Lcrit ~ 1cm EE141 EECS141 12 Lecture #25 EE141 Classes of Parasitics  Reduce Robustness  Affect Performance • Capacitive • Resistive • InductiveEE141 7 EE141 EECS141 13 Lecture #25 3 x 1 µm overlap: 0.19 V disturbance EE141 EECS141 14 Lecture #25 τXY = RY(CXY+CY) Keep time-constant smaller than rise time V (Volt) 0 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 1 0.8 0.6 t (nsec) 0.4 0.2 X Y V X R Y C XY C Y tr↑EE141 8 EE141 EECS141 15 Lecture #25  Avoid floating nodes  Protect sensitive nodes  Make rise and fall times as large as possible  Differential signaling  Do not run wires together for a long distance  Use shielding wires  Use shielding layers EE141 EECS141 16 Lecture #25 Cc - Impact of neighboring signal activity on switching delay - When neighboring lines switch in opposite direction of victim line, delay increasesEE141 9 EE141 EECS141 17 Lecture #25 r is ratio between capacitance to GND and to neighbor EE141 EECS141 18 Lecture #25  Both delay and power are reduced by dropping interconnect capacitance  Types of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k)  The numbers below are on the conservative side of the NRTS roadmap εEE141 10 EE141 EECS141 19 Lecture #25  Avoid large crosstalk cap’s  Avoid floating nodes  Isolate sensitive nodes  Control rise/fall times  Shield!  Differential signaling EE141 EECS141 20 Lecture #25 V in V out C L V DD • Transistor Sizing • Cascaded BuffersEE141 11 EE141 EECS141 21 Lecture #25 CL = 20 pF In Out 1 2 N 0.25 µm process Cin = 2.5 fF tp0 = 30 ps F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns EE141 EECS141 22 Lecture #25 Trade off Performance for Area and Energy Given tpmax find N and f  Area  EnergyEE141 12 EE141 EECS141 23 Lecture #25 10 1 3 5 7 Number of buffer stages N 9 11 10,000 1000 100 F = 100 F = 1000 F = 10,000 tp/tp0 EE141 EECS141 24 Lecture #25 Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns 0.25 µm process, CL = 20 pFEE141 13 EE141 EECS141 25 Lecture #25 Bonding Pad Out In VDD GND 100 µm GND Out EE141 EECS141 26 Lecture #25  When a chip is connected to a board, there is unknown (potentially large) static voltage difference  Equalizing potentials requires (large) charge flow through the pads  Diodes sink this charge into the substrate – need guard rings to pick it up.EE141 14 EE141 EECS141 27 Lecture #25 Diode PAD V DD R D 1 D 2 X C EE141 EECS141 28 Lecture #25 • Bond wires (~25µm) are used to connect the package to the chip • Pads are arranged in a frame around the chip • Pads are relatively large (~100µm in 0.25µm technology), with large pitch (100µm) • Many chips areas are ‘pad limited’ Chip L L ´ Bonding wire Mounting cavity Lead frame PinEE141 15 EE141 EECS141 29 Lecture #25 Layout Die Photo EE141 EECS141 30 Lecture #25 Clock is distributed in a tree-like fashion H-tree CLKEE141 16 EE141 EECS141 31 Lecture #25 [Restle98] EE141 EECS141 32 Lecture #25 • No rc-matching • Large powerEE141 17 EE141 EECS141 33 Lecture #25 EE141 EECS141 34 Lecture #25  2 phase single wire clock, distributed globally  2 distributed driver channels  Reduced RC delay/skew  Improved thermal distribution  3.75nF clock load  58 cm final driver width  Local inverters for latching  Conditional clocks in caches to reduce power  More complex race checking  Device variation trise = 0.35ns tskew = 150ps tcycle= 3.3ns Clock waveform Location of clock driver on die pre-driver final driversEE141 18 EE141 EECS141 35 Lecture #25 EE141 EECS141 36 Lecture #25EE141 19 EE141 EECS141 37 Lecture #25  2 Phase, with multiple conditional buffered clocks  2.8 nF clock load  40 cm final driver width  Local clocks can be gated “off” to save power  Reduced load/skew  Reduced thermal issues  Multiple clocks complicate race checking trise = 0.35ns tskew = 50ps tcycle= 1.67ns Global clock waveform EE141 EECS141 38 Lecture #25EE141 20 EE141 EECS141 39 Lecture #25 GCLK Skew (at Vdd/2 Crossings) ps 5 10 15 20 25 30 35 40 45 50 ps 300 305 310 315 320 325 330 335 340 345 GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%) EE141 EECS141 40 Lecture #25 + widely dispersed drivers + DLLs compensate static and low-frequency variation + divides design and verification effort - DLL design and verification is added work + tailored clocks Active Skew Management and Multiple Clock DomainsEE141 21 EE141 EECS141 41 Lecture #25 Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 2) Ordering of events is implicit in logic 1) Completion is ensured by careful timing analysis Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol EE141 EECS141 42 Lecture #25EE141 22 EE141 EECS141 43 Lecture #25  We have already learned how to drive RC interconnect  Impact of resistance is commonly seen in power supply distribution:  IR drop  Voltage variations  Power supply is distributed to minimize the IR drop and the change in current due to


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Berkeley ELENG 141 - Lecture25 - Interconnect

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