Report_AB20_Proj-1.pdfDejan Markovic EECS 141 Project 1 Report for Groups A20 and B20 (max 4 pages)EECS141: FALL 05—PROJECT 1 1 UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering, Department of EECS Dejan Markovic EECS 141 Fall 2005 Project 1 Report for Groups A20 and B20 (max 4 pages) Name (Last, First) Student ID Design GroupGood Report EE141 Project 1 Fall 2005 A20 Summary of results from Phase-1 Design x1 x2 x3 y1 y2 y3 Baseline 1 2 3 2.82 2.82 2.82 Dmin (tp0) = 18.60 Eref = 277.39 CgateVdd2 Summary of results from Phase-2 Design x1 x2 x3 y1 y2 y3 Optimized 1 1.26 1.51 1.53 1.45 1.27 Delay Dmin 1.1Dmin 1.2Dmin Energy reduction (%) Sub-design 18.60 20.46 22.32 14.99 Summary of results from Phase-3 Dmin (ps) Eref (nJ) D inc (%) E red (%) 427.8 9.88 · 10-3 9.43 19.2 Scoreboard Phase-1 Phase-2 Phase-3 TotalPhase 1: Baseline Design Summary of results from Phase-1 Design x1x2x3y1y2y3Baseline 1 2 3 2.82 2.82 2.82 Dmin (tp0) = 18.60 Eref = 277.39 CgateVdd2 Phase I: Our goal is to minimize the maximum delay of the three branches from Vin to the load capacitor, CL. As we learned from lecture, we want to make the delay through each period (tp1, tp2, and tp3) the same through all three branches. The delay formulas of the three branches are listed as follows (with the assumption that slope of the input signal is the same as slope of output signal): 2 tp1 tp2 tp3 -------------------- --------------- ---------------- ⎥⎦⎤⎢⎣⎡⋅++⋅⋅+++++= )11.1161()11.121()11.11(1113210yxyxxxtDpA ⎥⎦⎤⎢⎣⎡⋅++⋅⋅+++++= )11.1161()11.141()11.11(2223210yxyxxxtDpB ⎥⎦⎤⎢⎣⎡⋅++⋅⋅+++++= )11.1161()11.161()11.11(3333210yxyxxxtDpC Solving the optimal width: 1. tp3a= tp3b= tp3c: 321321)11.1161()11.1161()11.1161( yyyyyy==⇒⋅+=⋅+=⋅+ 2. 3:2:1::)11.161()11.141()11.121(321332211=⇒⋅⋅+=⋅⋅+=⋅⋅+ xxxxyxyxy 3. Since , CBADDD == )min()),,min(max(ACBADDDD=, so we take the partial derivative of respect to and . AD1x1y011.1211.1621101=⎥⎦⎤⎢⎣⎡⋅⋅+=∂∂xytxDpA, 011.11611.1221101=⎥⎦⎤⎢⎣⎡⋅+⋅=∂∂yxtyDpA. Solving the two equations above, we got umx 96.01= andumy 77.21=, but we have the constraint that all the widths have to be greater or equal to 1um. We then switched to Microsoft Excel to solve for the optimal widths to minimize our delays (by using the ratio of x and y we got from taking differentiation). The table below shows the width values we got from using the solver. With all the width values, we can calculate Eref, total Cap, and Dmin, which is on the right side of the table. Ind. Variables Optimal Width (um) Dep. Variables Dep. Values x1 1 total Cap (Cgate) 277.39 x2 2 Eref (Cgate) 277.39 Vdd2x3 3 Energy Consumption (J) 9.71E-12 y1 2.83 y2 2.83 Dmin/tp0 18.60 y3 2.83 Dmin (ps) 468.11Phase 2: Optimized Design Summary of results from Phase-2 Design x1x2x3y1y2y3Optimized 1 1.26 1.51 1.53 1.45 1.27 Delay Dmin1.1Dmin1.2DminEnergy reduction (%) Sub-design 18.60 20.46 22.32 14.99 In phase II, our goal was to minimize energy while allowing for a mismatch in delays between the three branches. We began by writing the equation for energy in a cycle: E = Ccycle×Vdd2. We wanted energy in terms of Cgate and Vdd to compare it to Eref of phase 1, where γ = Cintrinsic/Cgate = 1.11. We calculated Ccycle by calculating the intrinsic and gate capacitance seen at each node as shown below: CBAgategatecycleCCCCxxxCC+++⋅+++⋅= )(321γ Branch A: )(22111 LgategategateACCyCyCxC+⋅⋅⋅+⋅⋅+⋅⋅=γγ Branch B: )(44222 LgategategateBCCyCyCxC+⋅⋅⋅+⋅⋅+⋅⋅=γγ Branch C: )(66333 LgategategateCCCyCyCxC+⋅⋅⋅+⋅⋅+⋅⋅=γγ After we had a formula for Ccycle, we saw that in order to decrease the overall energy, we wanted to assign the greatest amount of delay, Dmin×1.2, to branch C. As shown by the equation for Cc, y3 adds the most capacitance because it is involved in six branches, and is consequently multiplied by the greatest factor. Thus, we wanted to assign the largest delay to this branch: ⎥⎦⎤⎢⎣⎡⋅++⋅⋅+++++= )11.1161()11.161()11.11(3333210yxyxxxtDpC By increasing DC it will allow y3 to become small since the last term has y3 in the denominator. The y3 in the second term is not as important because it is offset by x3, which can be changed as DC increases. Once we had these constraints set, we inputted the equations into Excel and solved for the minimum Ccycle with the constraints of xi and yi ≥1, DA ≤ Dmin of phase 1, DB ≤ 1.1×DBmin, and DC ≤ 1.2×Dmin. The table below summarizes our results from Excel: Ind. Variables Optimal Width (um) Dep. Variables Dep. Values x1 1 total Cap (Cgate) 235.81 x2 1.26 Eref (Cgate) 235.81×Vdd2x3 1.51 Energy Consumption (J)8.25E-12 y1 1.53 y2 1.45 y3 1.27 Delay Delay/tp0 Delay (ps) DA/tp0 18.60 DA 468.11 DB/tp0 B20.46 DB B514.92 DC/tp0 22.32 DC 561.73 We tested our assumption that branch C required the largest delay in Excel by setting the constraints as DA ≤ 1.2×Dmin, DB ≤ 1.1×DBmin, and DC ≤ Dmin, and found the total capacitance to be greater; thus, our initial assumption was correct. 3Phase 3: HSPICE Verification Summary of results from Phase-3 Dmin (ps) Eref (nJ) D inc (%) E red (%) 427.8 9.88 x 10-39.43 19.2 Considerations for SPICE Simulation: 1. Add three unit-size inverters at the beginning to ensure realistic input signal slope. 2. Normalize all the inverters to unit-size by using the “m” tag. (eg. If width = 2.9um, then use width=0.97um and m=3 instead of width=2.9um and m=1), since that was our assumption when we did our hand calculations. 3. Add a big inverter after the 16x inverter to suppress miller kick-back effect (because the input won’t track the output node very well with a big capacitor). 4. Use different voltage sources for those inverters where we don’t want to measure energy. 5. Look at the current through each node of interest and compare it with the values we got directly from Vdd. 6. Look at the delay and rise/fall time of each inverter and see if it is bigger or smaller than what we expected. Phase I: Simulation Delay: 427.8ps Hand Calculation Delay: 468.1ps Difference: 40.3ps % Difference: 8.6% Why is there such big discrepancy? We went in and measured the rise/fall time of
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