Dejan Markovic EECS 141Project 1 (Group A10)Due Monday, October 31st, 5pmUNIVERSITY OF CALIFORNIACollege of EngineeringDepartment of Electrical Engineering and Computer SciencesDejan Markovic EECS 141Fall 2005Project 1 (Group A10)Due Monday, October 31st, 5pme-mail to [email protected] (preferred) or turn in paper copy in 240 CoryProject DescriptionConsider a clock distribution network shown in Fig. 2. Your task is to optimize this circuit toensure correct timing of the chip, which consists of three sub-designs (A, B, and C). These sub-designs vary in complexity, so the total load varies. Assuming that each of the y inverters candrive a fanout of CL, we need nk (k = 1, 2, 3) branches to drive the total clock load of nk·CL. Weignore the wiring capacitance (which is an important component of any real clock distributionnetwork), and ignore the delay of the wires. Parameters: n1 = 2, n2 = 4, n3 = 6, CL = 16.x21y2CLClkn2y2CLx1y1CLn1y1CLA Bx3y3CLn3y3CLCFigure 2: Clock Distribution NetworkYou are given technology parameters tp0 = 25.17ps and = Cintrinsic/Cgate = 1.11 for delayanalysis in Phase-3. These parameters are extracted using the methodology outlined in Problem2 of your Project tips & background document. Unit sized inverter has following parameters:Wp = 2m, Wn = 1m, Lp = Ln = 0.25m.EECS141: FALL 05—PROJECT 1 1Phase 1: Baseline Design (1/2 week)Determine the sizes xk 1 and yk 1 (k = 1, 2, 3) of the clock inverters to achieve minimumworst-case propagation delay from Clk to all the clock sinks. Propagation delay from Clk to thefinal clock load is often times referred to as the insertion delay. What is the value of Dminnormalized to tp0? This will be your reference delay for Phase-2.What is the energy Eref dissipated from power supply during a full 010 switching cycle?Express the energy symbolically in terms of Cgate of the unit sized inverter (label Cgate = C to keepit simple) and supply voltage VDD. Now, you have obtained reference point (Dmin, Eref) for youroptimizations.Phase 2: Optimized Design (1 week)Now, assume that you are allowed to tolerate slight mismatch in insertion delays. New targetinsertion delays for the three sub-designs are Dmin, 1.05Dmin, 1.1Dmin. The first goal is to assignthese delays to blocks A, B, and C with energy minimization in mind and then perform re-sizingof the gates to minimize energy dissipated by the clock tree.a) What is the optimal assignment of Dmin, 1.05Dmin, 1.1Dmin to A, B, and C?b) What are the optimal sizing factors xk 1 and yk 1 (k = 1, 2, 3)?c) Calculate percent energy reduction compared to the reference energy Eref .Phase 3: Verification in HSPICE (1/2 week)Verify your results from previous two phases in HSPICE.a) Obtain reference point (Dmin, Eref) in HSPICE. Is it different from what you expected?(Hint: CD and CE from Background Problem 1 could help, but this is not the only reason!)b) Using gate size parameters from Phase-2, report simulated delay increase and energyreduction. Determine these numbers relative to the reference case (Dmin, Eref) obtained byHSPICE in part (a) of Phase-3. Comment your results.ReportPlease use the report template provided at the web-site. Be sure to justify important designdecisions and emphasize all the vital information. Organization, conciseness, and completenessare of paramount importance. Make sure to fill out the cover-page and use the correct units.GradingFor each phase, the grade will be divided as follows:30% result30% correctness40% approach and reportEECS141: FALL 05—PROJECT 1
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