EE141 HW5 Solution-Spring 2008P1) The functionalities are for (a) /Z=AB+C(/B), for (b) /Z=A(/B)+(/A)B, for(c)/Z=A+BC. The pull up networks are shown below.P2) The exprresion can be simplified noting that C(/D)+CD=C(D+/D)=C*1=C so that the expression becomes eitherZ=/(/A /B /C)or the equivalentZ=A+B+CExpression 1 is NAND-based and therefore will have lower delay. Let usperform logical effort anlysis:the chain has no branching, so B=1. Similarly, F=64 and G=5/3 (This is thelogical effort for a three input NAND). The total effort is 64*5/3=106 andtherefore the per-stage effort should be 1060.5=10.32As a result, the inverter driving strength should be 10.32X and the inputinverters should be sized for unit strength.P3)For a) since the XORs are symmetric gates, they have p0=p1=0.5 at theiroutputs., so p0->1=1/4 For the NAND gate, the probability of the outputbeing at one is the probability that both inputs will be at 1 at the same timeand so for this case(symmetric inputs) p1=1/4 and p0-1=3/16.So Pd=1/4 fsVdd2(C1+C2+3/4C3)For b) similarly, we have p1=1/8,p0=7/8 so that p0-1=7/64 and Pd=7/64 CfsVdd2For c) the activity at the output of the NAND gate is calculated as before as3/16, while that at the output of the OR gate requires more care. Inparticular, since the input to the gate are both equally likely to be 0 or 1, weneed to use the fact that the output of an OR gate is 0 if and only if bothinputs are 0. Thereforep0=p0a*p0b=3/4*1/2=3/8 and p0->1=15/64. The total power is Pd= fsVdd2(15/64 C1+3/16 C2) = fsVdd2(C1+C2) 7/64 ( 15/7*C1/(C1+C2)+12/7*C2/(C1+C2) ) > fsVdd2(C1+C2) 3/16 > fsVdd2(C1+C2) 7/64. Therefore theimplementation with a single NAND gate is more power efficient for thiscapacitance distribution.Intuitively, the switching activity of the 3-NAND is the lowest of all gates,which is why the power is
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