EECS 141: FALL2002 – MIDTERM 2 1/7 University of California College of Engineering Department of Electrical Engineering and Computer Sciences B. Nikolić Thursday, November 7, 2002 6:00-7:30pm EECS 141: FALL 2002—MIDTERM 2 For all problems, you can assume the following transistor parameters (unless mentioned otherwise): NMOS: VTn = 0.4, k’n = 115 µA/V2, VDSAT = 0.6V, λ = 0, γ = 0.4 V1/2, 2ΦF = −0.6V PMOS: VTp = −0.4V, k’p = 30 µA/V2, VDSAT = −1V, λ = 0, γ = -0.4 V1/2, 2ΦF = 0.6V NAME LastFirstGRAD/UNDERGRAD Problem 1: _____/16 Problem 2: _____/12 Problem 3: _____/10 Problem 4: _____/ 6 Total: _____/44EECS 141: FALL2002 – MIDTERM 2 2/7 PROBLEM 1. Logic Styles (16pts) In this problem, for single-ended logic styles, assume that only true inputs are available, and for differential logic styles you can use both true and complementary inputs. Draw a gate implementing Y = AB + CD in: a) Standard complementary CMOS. b) Domino logic.EECS 141: FALL2002 – MIDTERM 2 3/7 c) Dual-rail domino. d) Transmission-gate logic (differential logic style)EECS 141: FALL2002 – MIDTERM 2 4/7 PROBLEM 2. Logical effort. (12pts) a) (4pts) Find the logical effort for a domino buffer from the figure. Assume that the static inverter PMOS/NMOS ratio is appropriately skewed. φφInOutFig. 1. g =EECS 141: FALL2002 – MIDTERM 2 5/7 b) (8pts) Calculate the optimal stage effort (product of the logical effort and fanout) for the domino buffer with a foot switch (as one shown in Fig.1). (Hint: we calculated that the optimal effort for the static complementary CMOS stage is about 4. Recalculate this for the domino buffer that consists of a dynamic inverter and a skewed static inverter). Optimal fanout =EECS 141: FALL2002 – MIDTERM 2 6/7 PROBLEM 3: Arithmetic Circuits (10pts) Consider an implementation of a bit-sliced 32-bit carry-lookahead adder implemented in static CMOS. The bit slice is 18 metal pitch, and the metal pitch is 1um. You can assume that the resistance of all metal layers is 0.1Ω/□. The table below shows the dependence of the intra-layer capacitance per unit length for the metal layer that is used for implementation of this carry wire. Spacing Min 1.5 * Min 2 * Min 2.5* Min 3 * Min or more Capacitance 80aF/µm 60aF/µm 50aF/µm 45aF/µm 40aF/µm a) (2pts) How many bit slices does the longest carry wire cross in radix-2 implementation? b) (2pts) How many bit slices does the longest carry wire cross in radix-4 implementation? c) (2pts) What is the worst-case coupling capacitance of the wire when all the carries are routed vertically with double-width, double-spaced pitch? d) (2pts) How does this capacitance change if the wire pitch is doubled from the previous case, without changing the wire width? e) (2pts) If the shielding wires are introduced in the same layer as shown before, what is the worst-case coupling capacitance? Carryi Carryi+1 2Wmin 2WminCarryi Shield 2Wmin 2WminCarryi+1 2Wmin2WminCtotal = Ctotal = Ctotal =EECS 141: FALL2002 – MIDTERM 2 7/7 PROBLEM 4. Power dissipation (6 pts). Compute the probability of the energy consuming transitions of the output, F of the logic function CBAF ⋅+= , implemented in standard static CMOS, if the input probabilities are p(A=1) = 0.2, p(B=1) = 0.5, p(C=1) =
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