1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on April 25, 2003 by Dejan Markovic ([email protected]) Prof. Jan Rabaey EECS 141 Spring 2003 Homework 10 Due Thu, May 1, 5pm @ 558 Cory Problem 1. Timing & Race Conditions The following circuit consists of a source portion which adds the outputs of two registers R1 & R2 and a destination portions which stores the sum in R3. The connections between the source and the destination are made by an automatic router which creates wires with an average length of 1mm and containing an average of 10 contact holes in series. This leads to a resistance of about 200 Ω and capacitance of about 100 fF for each wire. A clock driver buffers the clock signal at the source and is routed by the same tool to the destination, where it connects to R3 and two other registers (R4 & R5) which happen to be close by. Each register presents a load of 300 fF to the clock driver. Figure 1. Circuit for problem 1. Assume the following timing values for the logic: tcarry = 250 ps, tsum = 300 ps (including the wire load), tsetup = 150 ps, thold = 100 ps, tclk-Q = 50 ps. a) Does this circuit have a race problem? What is the minimum clock period? b) What if you removed R4 and R5? Would there be a race problem? What would the new minimum clock period be? c) What if the driver were placed at the destination (with R3,R4 & R5)? Would there be a race problem? What would the new minimum clock period be? 32-bit Reg. 32-bit Reg. 32-bit Reg. ABCICO SUM ABCICO SUM ABCICO SUM 32-bit Adder32-bit Reg. 32-bit Reg. ~1 mm Wire200 Ω 100 fFClock Driver 150 Ω Source Destination2 Problem 2: Oscillator An oscillator is shown in Figure 2. Draw the signal waveforms for this circuit at nodes X, Y, Z, A, and B. Determine the oscillation frequency. Discuss the advantage of this circuit. You may assume that the delay of the inverters, the resistances of the MOS transistors, and all internal capacitors can be ignored. The inverter switch point is set at 1.65V. Assume that nodes Y and Z are initially at 0V and 3.3V, respectively. Figure 2: An oscillator. Problem 3. Monostable Multivibrator Consider the monostable multivibrator circuit drawn below. Calculate the output pulse width. You are given following transistor parameters: Vt(depletion transistor) = -0.5V, Vt = 0.4 V, K’ = 100µA/V2, γ = 0. Assume Vin has been 0 for sometime and then suddenly switches to 2.4V. How wide is the pulse at the output (i.e. how long is Vout high)? Assume that the output switches when the voltage on the gate input to the driver crosses 1.2 V. Initially the output is low, so the driver is on. Then when Vin goes high, the driver turns of. Assume that the driver turns on again when its gate input voltage reaches 1.2V. Figure 3. Monostable multivibrator.3 Problem 4. Timing Analysis Consider the following simple processor, consisting of a pipelined data path and a finite-state machine based controller. RF, PR, and IR denote edge-triggered flip-flops, while DP1, DP2, and FSM denote logic modules. Minimum and maximum delays of the modules are shown in the table next to the Figure. You may ignore the delay of the interconnect as well as the delays of the registers. The δ’s at the clock inputs of the registers denote the absolute skew between the clock source and the register. Figure 4. Simple processor. Min Delay Max Delay DP1 3 10 DP2 2 8 FSM 1 5 a) Write down the necessary constraints on the clock skews to avoid race conditions. b) Derive the constraints on the clock period in the presence of skew. c) Determine minimum possible clock period. d) Determine the values of the skews for which this minimum period is achieved. e) Propose a revised architecture that would reduce the clock period (changing circuit style is not an option). Explain your design, and discuss the disadvantages of your approach. δ1 δ2 δ3 RF DP1 DP2 FSM
View Full Document
Unlocking...