EE1411EE1411EE141-S04EE141EE141--Spring 2004Spring 2004Digital Integrated Digital Integrated CircuitsCircuitsLecture 28Lecture 28Semiconductor MemorySemiconductor MemoryEE1412EE141-S04Administrative StuffAdministrative Stuff Homework 10 posted – just for practice. No need to turn in. Poster presentations tomorrow. No lecture. Sign up for time slot (office door of Prof. Rabaey). Poster template on web-site. Last lecture on Th – overview of future trends in digital IC design. Project 2 + Final discussion. Also HKN review. Your feedback is important!EE1412EE1413EE141-S04MemoryMemoryEE1414EE141-S04Issues in MemoryIssues in Memory Memory Classification Memory Architectures The Memory Core Periphery Reliability Case StudiesEE1413EE1415EE141-S04Semiconductor Memory ClassificationSemiconductor Memory ClassificationRead-Write MemoryNon-VolatileRead-WriteMemoryRead-Only MemoryEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFOEE1416EE141-S04Memory Timing: DefinitionsMemory Timing: DefinitionsEE1414EE1417EE141-S04Memory Architecture: DecodersMemory Architecture: DecodersWord 0Word 1Word 2Word N22Word N21StoragecellM bits M bitsNwordsS0S1S2SN22A0A1AK21K5log2NSN21Word 0Word 1Word 2Word N22Word N21StoragecellS0Input-Output(M bits)Intuitive architecture for N x M memoryToo many select signals:N words == N select signalsK = log2NDecoder reduces the number of select signalsInput-Output(M bits)DecoderEE1418EE141-S04ArrayArray--Structured Memory ArchitectureStructured Memory ArchitectureEE1415EE1419EE141-S04Hierarchical Memory ArchitectureHierarchical Memory ArchitectureAdvantages:Advantages:1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savingsEE14110EE141-S04Block Diagram of 4 Block Diagram of 4 MbitMbitSRAMSRAMSubglobalrow decoderGlobal row decoderSubglobalrow decoderBlock 30Block 31128 K Array Block 0Block 1ClockgeneratorCS, WEbufferI/ObufferY-addressbufferX-addressbufferx1/x4controllerZ-addressbufferX-addressbufferPredecoder and block selectorBit line loadTransfer gateColumn decoderSense amplifier and write driverLocal row decoder[Hirose90]EE1416EE14111EE141-S04ReadRead--Only Memory CellsOnly Memory CellsWLBLWLBL1WLBLWLBLWLBL0VDDWLBLGNDDiode ROM MOS ROM 1 MOS ROM 2EE14112EE141-S04MOS OR ROMMOS OR ROMWL[0]VDDBL[0]WL[1]WL[2]WL[3]VbiasBL[1]Pull-down loadsBL[2] BL[3]VDDEE1417EE14113EE141-S04MOS NOR ROMMOS NOR ROMWL[0]GNDBL[0]WL[1]WL[2]WL[3]VDDBL[1]Pull-up devicesBL[2] BL [3]GNDEE14114EE141-S04MOS NOR ROM LayoutMOS NOR ROM LayoutProgrammming using theActive Layer OnlyPolysiliconMetal1DiffusionMetal1 on DiffusionCell (9.5λ x 7λ)EE1418EE14115EE141-S04MOS NOR ROM LayoutMOS NOR ROM LayoutPolysiliconMetal1DiffusionMetal1 on DiffusionCell (11λ x 7λ)Programmming usingthe Contact Layer OnlyEE14116EE141-S04MOS NAND ROMMOS NAND ROMAll word lines high by default with exception of selected rowWL[0]WL[1]WL[2]WL[3]VDDPull-up devicesBL[3]BL[2]BL[1]BL[0]EE1419EE14117EE141-S04MOS NAND ROM LayoutMOS NAND ROM LayoutNo contact to VDD or GND necessary;Loss in performance compared to NOR ROMdrastically reduced cell sizePolysiliconDiffusionMetal1 on DiffusionCell (8λ x 7λ)Programmming usingthe Metal-1 Layer OnlyEE14118EE141-S04NAND ROM LayoutNAND ROM LayoutCell (5λ x 6λ)PolysiliconThreshold-alteringimplantMetal1 on DiffusionProgrammming usingImplants OnlyEE14110EE14119EE141-S04Equivalent Transient Model for MOS NOR ROMEquivalent Transient Model for MOS NOR ROM Word line parasitics Wire capacitance and gate capacitance Wire resistance (polysilicon) Bit line parasitics Resistance not dominant (metal) Drain and Gate-Drain capacitanceModel for NOR ROMVDDCbitrwordcwordWLBLEE14120EE141-S04Equivalent Transient Model for MOS NAND ROMEquivalent Transient Model for MOS NAND ROM Word line parasitics Similar to NOR ROM Bit line parasitics Resistance of cascaded transistors dominates Drain/Source and complete gate capacitanceModel for NAND ROMVDDCLrwordcwordcbitrbitWLBLEE14111EE14121EE141-S04PrechargedPrechargedMOS NOR ROMMOS NOR ROMPMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.WL[0]GNDBL[0]WL[1]WL[2]WL[3]VDDBL[1]Precharge devicesBL[2] BL[3]GNDprefEE14122EE141-S04NonNon--Volatile MemoriesVolatile MemoriesThe FloatingThe Floating--gate transistor (FAMOS)gate transistor (FAMOS)Floating gateSourceSubstrateGateDrainn+n+_ptoxtoxDevice cross-sectionSchematic symbolGSDEE14112EE14123EE141-S04FloatingFloating--Gate Transistor ProgrammingGate Transistor Programming0 V25 V0 VDSRemoving programming voltage leaves charge trapped5 V22.5 V5 VDSProgramming results inhigher VT.20 V10 V 5 V20 VDSAvalanche injectionEE14124EE141-S04A “ProgrammableA “Programmable--Threshold” TransistorThreshold” TransistorAdo be Sy stemsEE14113EE14125EE141-S04FLOTOX EEPROMFLOTOX EEPROMFloating gateSourceSubstratepGateDrainn1n1FLOTOX transistorFowler-NordheimI-V characteristic20–30 nm10 nm-10 V10 VIVGDEE14126EE141-S04EEPROM CellEEPROM CellWLBLVDDAbsolute threshold controlis hardUnprogrammed transistor might be depletionÖ 2 transistor cellEE14114EE14127EE141-S04Flash EEPROMFlash EEPROMControl gateerasurep-substrateFloating gateThin tunneling oxiden1sourcen1drainprogrammingMany other options …EE14128EE141-S04CrossCross--sections of NVM cellssections of NVM cellsEPROMFlashCourtesy IntelEE14115EE14129EE141-S04Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――EraseEraseEE14130EE141-S04Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――WriteWriteEE14116EE14131EE141-S04Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――ReadReadEE14132EE141-S04NAND Flash MemoryNAND Flash MemoryUnit CellWord line(poly)Source line(Diff. Layer)Courtesy ToshibaAdo be Sy stemsEE14117EE14133EE141-S04NAND Flash MemoryNAND Flash MemoryWord linesSelect transistorBit line contact Source line contactActive areaSTICourtesy ToshibaEE14134EE141-S04ReadRead--Write Memories (RAM)Write Memories (RAM) STATIC (SRAM) DYNAMIC (DRAM)Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferentialPeriodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle EndedEE14118EE14135EE141-S0466--transistor CMOS SRAM Cell transistor CMOS SRAM Cell WLBLVDDM5M6M4M1M2M3BLQQEE14136EE141-S04CMOS SRAM
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