1EE141CMOS LogicEE141- Spring 2003Lecture 13EE141AnnouncementsMidterms ResultsProject LaunchLast software lab this weekNew homework on Th2EE141Today’s lectureTransmission LinesCMOS LogicEE141The Transmission LineVinrlcrlcrlcrlcVoutxg g g gThe Wave Equation3EE141Wave Reflection for DifferentTerminationsEE141Transmission Line Response (RL= ∞)0.01.02.03.04.05.0V0.01.02.03.04.0V0.0 5.0 10.0 15.0t(intlightf)0.02.04.06.08.0VRS=5Z0RS=Z0RS=Z0/5(a)(b)(c)VDestVSource4EE141Lattice DiagramVSourceVDest0.8333 V1.6666 V+ 0.8333+0.8333+ 0.5556+0.5556+ 0.3704+ 0.2469+0.3704+0.24692.2222 V3.1482 V3.7655 V...2.7778 V3.5186 V4.0124 VL/νtEE141Critical Line Lengths versus Rise Times(1990, Bakoglu)100-200ps todayLcrit~1cm5EE141Design Rules of ThumbTransmission line effects should be considered when therise or fall time of the input signal (tr,tf) is smaller than thetime-of-flight of the transmission line (tflight).tr(tf)<<2.5tflightTransmission line effects should only be considered whenthe total resistance of the wire is limited:R<5Z0The transmission line is considered lossless when the totalresistance is substantially smaller than the characteristicimpedance,R<Z0/2EE141Should we be worried?Transmission line effectscause overshooting and non-monotonic behaviorClock signals in 400 MHz IBM Microprocessor(measured using e-beam prober) [Restle98]6EE141CMOS LogicStatic CMOSConventional Static CMOS LogicRatioed LogicPass Transistor/Transmission Gate LogicDynamic CMOS LogicDominonp-CMOSEE141Combinational vs. Sequential LogicLogicCircuitLogicCircuitOutOutInIn(a) Combinational (b) SequentialStateOutput =f(In)Output =f(In, Previous In)7EE141Static CMOS CircuitAt every point in time (except during the switchingtransients) each gate output is connected to eitherVDDorVssvia a low-resistive path.The outputs of the gates assume at all times the valueof the Boolean function, implemented by the circuit(ignoring, once again, the transient effects duringswitching periods).This is in contrast to the dynamic circuit class, whichrelies on temporary storage of signal values on thecapacitance of high impedance circuit nodes.EE141Static Complementary CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPMOS onlyNMOS onlyPUN and PDN are dual logic networks……8EE141NMOS Transistors in Series/ParallelConnectionTransistors can be thought as a switch controlled by its gate signalNMOS switch closes when switch control input is highXYABY=XifAandBXYABY=XifAORBNMOS Transistors pass a “strong” 0 but a “weak” 1EE141PMOS Transistors in Series/ParallelConnectionXYABY=X ifAAND B =A+BXYABY=XifAOR B =ABPMOS Transistors pass a “strong” 1 but a “weak” 0PMOS switch closes when switch control input is low9EE141Threshold DropsVDDVDD→ 0PDN0 → VDDCLCLPUNVDD0 → VDD-VTnCLVDDVDDVDD→ |VTp|CLSDSDVGSSSDDVGSEE141Complementary CMOS Logic Style Construction10EE141Example Gate: NANDEE141Example Gate: NOR11EE141Complex CMOS GateOUT = D + A • (B + C)DABCDABCEE141Cell DesignStandard Cells» General purpose logic» Can be synthesized» Same height, varying widthDatapath Cells» For regular, structured designs (arithmetic)» Includes some wiring in the cell» Fixed height and width12EE141Standard Cell LayoutMethodology – 1980ssignalsRoutingchannelVDDGNDEE141Standard Cell LayoutMethodology – 1990sM2No RoutingchannelsVDDGNDM3VDDGNDMirrored CellMirrored Cell13EE141Standard CellsCell boundaryNWellCell height 12 metal tracksMetal track is approx. 3λ +3λPitch =repetitive distance between objectsCell height is “12 pitch”2λRails ~10λInOutVDDGNDEE141Standard CellsInOutVDDGNDIn OutVDDGNDWith silicideddiffusionWith minimaldiffusionroutingOutInVDDM2M114EE141Standard CellsAOutVDDGNDB2-input NAND gateBVDDAEE141Stick DiagramsContains no dimensionsRepresents relative positions of transistorsInOutVDDGNDInverterAOutVDDGNDBNAND215EE141Stick DiagramsCABX=C•(A+B)BACijjVDDXXiGNDABCPUNPDNABCLogic GraphEE141Two Versions of C • (A + B)XCAB ABCXVDDGNDVDDGND16EE141Consistent Euler PathjVDDXXiGNDABCABCEE141OAI22 Logic GraphCABX = (A+B)•(C+D)BADVDDXXGNDABCPUNPDNCDDABCD17EE141Example: x = ab+cdGNDxabcdVDDxGNDxabcdVDDx(a) Logic graphs for (ab+cd)(b) Euler Paths {abcd}acdxVDDGND(c) stick diagram for ordering {abcd}bEE141Multi-Fingered TransistorsOne fingerTwo fingers (folded)Less capacitance18EE141Properties of Complementary CMOS GatesSnapshotHigh noise margins:VOHand VOLare at VDDand GND, respectively.No static power consumption:There never exists a direct path between VDDandVSS(GND) in steady-state mode.Comparable rise and fall times:(under appropriate sizing conditions)EE141CMOS PropertiesFull rail-to-rail swing; high noise marginsLogic levels not dependent upon the relativedevice sizes; ratiolessAlwaysapathtoVddorGndinsteadystate;low output impedanceExtremely high input resistance; nearly zerosteady-state input currentNo direct path steady state between powerand ground; no static power dissipationPropagation delay function of loadcapacitance and resistance of
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