EE141-Spring 2008 Digital Integrated CircuitsAnnouncementsClass MaterialReview: “Long-Channel” TransistorReview: “Short-Channel” TransistorReview: “Short-Channel” TransistorReview: “Short-Channel” TransistorCMOS Inverter VTCThe CMOS InverterPMOS Load LinesCMOS Inverter Load Characteristics CMOS Inverter VTC CMOS Inverter VTC Switching Threshold as a Function of Transistor RatioSwitching Threshold as a Function of Transistor RatioDetermining VIH and VILGain as a function of VDDImpact of SizingImpact of Process VariationsCMOS SwitchingMOS Transistor as a Switch MOS Transistor as a SwitchTransistor Driving a CapacitorSwitching DelaySwitching Delay (with Output Conductance)RC ModelFinding Req The Book’s Method The Transistor as a SwitchThe Transistor as a SwitchEE141EECS1411Lecture #6EE141EE141--Spring 2008Spring 2008 Digital Integrated Digital Integrated CircuitsCircuitsLecture 6Lecture 6Inverter VTC and DelayInverter VTC and DelayEE141EECS1412Lecture #6AnnouncementsAnnouncements Prof. Rabaey back next week Make-up lectures (will be video-taped) Tu Febr 19 – 11am-12:30pm Tu Febr 26 – 11am-12:30pm No Lab on Mo Febr 18 (President’s Day). Lab 3 starts on Tu Febr 19 Homework #3 due We Febr 20 (due to delayed schedule) Homework #4 posted that same dayEE141EECS1413Lecture #63Class MaterialClass Material Last lecture MOS transistor modeling Today’s lecture CMOS Inverter: VTC and delay Reading (5.1-5.3, 5.4.2)EE141EECS1414Lecture #6Review: Review: ““LongLong--ChannelChannel”” TransistorTransistorEE141EECS1415Lecture #6Review: Review: ““ShortShort--ChannelChannel”” TransistorTransistorEE141EECS1416Lecture #6Review: Review: ““ShortShort--ChannelChannel”” TransistorTransistorEE141EECS1417Lecture #6Review: Review: ““ShortShort--ChannelChannel”” TransistorTransistorEE141EECS1418Lecture #6CMOS InverterCMOS Inverter VTCVTCEE141EECS1419Lecture #69The CMOS InverterThe CMOS InverterVinVoutVDDWp = βWnWnEE141EECS14110Lecture #6PMOS Load LinesPMOS Load Lines For DC VTC, IDn= IDp Graphically, looking for intersections of NMOS and PMOS IV characteristics To put IV curves on the same plot, PMOS IV is “flipped” since |VDSp| = VDD–Vout Also, |VGSp| = Vdd-VinVDSp|IDp |Vin= 0Vin= 1.5VoutIDnVin= 0Vin= 1.5IVin= 2.5Vout (=VDSn )Vin= 1.5IDnEE141EECS14111Lecture #6CMOS Inverter Load CharacteristicsCMOS Inverter Load CharacteristicsIDnVoutVin = 2.5Vin = 2Vin = 1.5Vin = 0Vin = 0.5Vin = 1NMOSVin = 0Vin = 0.5Vin = 1Vin = 1.5Vin = 2Vin = 2.5Vin = 1Vin = 1.5PMOSEE141EECS14112Lecture #6CMOS Inverter VTCCMOS Inverter VTCVoutVin0.5 1 1.5 2 2.50.5 1 1.52 2.5NMOS resPMOS offNMOS offPMOS resNMOS satPMOS resNMOS resPMOS satNMOS satPMOS satEE141EECS14113Lecture #6CMOS Inverter VTCCMOS Inverter VTCVoutVin0.5 1 1.5 2 2.50.5 1 1.52 2.5NMOS resPMOS offNMOS offPMOS resNMOS satPMOS resNMOS resPMOS satNMOS satPMOS satEE141EECS14114Lecture #6Switching Threshold as a Function Switching Threshold as a Function of Transistor Ratioof Transistor Ratio1001010.80.911.11.21.31.41.51.61.71.8MV (V)Wp/Wn() ()dn M dp MIVIV=EE141EECS14115Lecture #6Switching Threshold as a Function Switching Threshold as a Function of Transistor Ratioof Transistor Ratio1001010.80.911.11.21.31.41.51.61.71.8MV (V)Wp/Wn22Solving for yields:22 with 1VSATpVSATnn VSATn M Tn p VSATp DD M TpMVSATpVSATnTn DD TppVSATppsatpMn VSATn n satnVVkV V V k V V V VVVVVrVVkVWVrrkVWυυ⎛⎞⎛⎞⎜⎟⋅−−=⋅ −−−⎜⎟⎜⎟⎝⎠⎝⎠⎛⎞⎛⎞⎜⎟++−−⎜⎟⎜⎟⎝⎠⋅⎝⎠===+⋅EE141EECS14116Lecture #6Determining VDetermining VIHIH and Vand VILILVOHVOLVinVoutVMVILVIHA simplified approachEE141EECS14117Lecture #6Gain as a function of VDDGain as a function of VDD0 0.05 0.1 0.15 0.200.050.10.150.2Vin (V)Vout (V)0 0.5 1 1.5 2 2.500.511.522.5Vin (V)Vout(V)Gain=-1EE141EECS14118Lecture #6Impact of SizingImpact of Sizing0 0.5 1 1.5 2 2.500.511.522.5Vin(V)Vout(V)Wider PMOSWider NMOSSymmetricalEE141EECS14119Lecture #6Impact of Process VariationsImpact of Process Variations0 0.5 1 1.5 2 2.500.511.522.5Vin(V)Vout(V)Fast PMOSSlow NMOSFast NMOSSlow PMOSNominalEE141EECS14120Lecture #6CMOS CMOS SwitchingSwitchingEE141EECS14121Lecture #6MOS Transistor as a Switch MOS Transistor as a Switch • We modeled this with:()DSDDvii =dtdVCiDSD=C• Discharging a capacitorCRtp = ln (2) RCEE141EECS14122Lecture #6MOS Transistor as a SwitchMOS Transistor as a Switch Saw that real transistors aren’t exactly resistors Look more like current sources in saturation Two questions: Which region of IV curve determines delay? How can that match up with the RC model?EE141EECS14123Lecture #6Transistor Driving a CapacitorTransistor Driving a Capacitor• With a step input:IDVDSVDDVDD /2VGS = VDDVDD Æ VDD/2VVSAT• Transistor is in (velocity) saturation during entire transition from VDD to VDD /2EE141EECS14124Lecture #6Switching DelaySwitching Delay• In saturation, transistor basically acts like a current source:IDSATCVOUTVOUT = VDD -(IDSAT /C)tVOUTtVDDVDD /2tptp = C(VDD /2)/IDSATEE141EECS14125Lecture #6Switching Delay Switching Delay (with Output Conductance)(with Output Conductance)()()11−−+ eDSAT-t C λIOUT DDV=Vλ- λ• Including output conductance:IDSATCVOUT1/(λIDSAT )()()21p≈+DDDDDSATCVtλVI• For “small” λ:EE141EECS14126Lecture #626RC ModelRC Model• Transistor current not linear on VOUT – how is the RCmodel going to work?• Look at waveforms:• Voltage looks like a ramp for RC too0 0.2 0.4 0.6 0.8 10.91.11.31.51.71.92.12.32.5t/τVOUTNMOSRCEE141EECS14127Lecture #627Finding Req Finding Req ()()(),21ppRC+DDeqDD DSATt=tCVRCλVI= ln 2()()( )21=+DDeqDD DSATVRλVIln 2• Match the delay of the RC model with the actual delay: • Often just: ()1≈⋅DDeqDSATVRI2ln2• Note that the book uses a different method and gets0.75·VDD /IDSAT instead of ~0.72·VDD /IDSAT . • Why did we do it this way vs. the book’s method?EE141EECS14128Lecture #6The BookThe Book’’s Method s MethodEE141EECS14129Lecture #6The Transistor as a SwitchThe Transistor as a Switch0.5 1 1.5 2 2.501234567x 105VDD (V)Req (Ohm)EE141EECS14130Lecture #6The Transistor as a SwitchThe Transistor as a
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