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Berkeley ELENG 141 - Lecture 21 Domino Logic

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EE1411EECS1411Lecture #21EE141EE141--Fall 2008Fall 2008Digital Integrated Digital Integrated CircuitsCircuitsLecture 21Lecture 21Domino LogicDomino LogicEE1412EECS1412Lecture #21AnnouncementsAnnouncements Project phase 2 out today, due next Fri.EE1413EECS1413Lecture #21Class MaterialClass Material Last lecture Dynamic logic Today’s lecture Domino logic Reading Chapter 7EE1414EECS1414Lecture #21Domino LogicDomino LogicEE1415EECS1415Lecture #21Domino LogicDomino LogicIn1In2PDNIn3MeMpClkClkOut1In4PDNIn5MeMpClkClkOut2Mkp1 → 11 → 00 → 00 → 1EE1416EECS1416Lecture #21Why Named Domino?Why Named Domino?ClkClkIniPDNInjIniInjPDNIniPDNInjIniPDNInjLike falling dominos!EE1417EECS1417Lecture #21Properties of Domino LogicProperties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition critical Input capacitance reduced – smaller logical effortEE1418EECS1418Lecture #21Domino Logic LEDomino Logic LEEE1419EECS1419Lecture #21Domino Logic LE (skewed static gate)Domino Logic LE (skewed static gate)EE14110EECS14110Lecture #21Buffer Buffer ““AverageAverage””LELEEE14111EECS14111Lecture #21Optimal EF/stage with DominoOptimal EF/stage with Domino Domino buffers are faster than static CMOS inverters Is optimal EF/stage for a chain of domino gates still 4?EE14112EECS14112Lecture #21Designing with Domino LogicDesigning with Domino LogicMpMeVDDPDNClkIn1In2In3Out1ClkMpMeVDDPDNClkIn4ClkOut2MrVDDInputs = 0during prechargeCan be eliminatedEE14113EECS14113Lecture #21Footless DominoFootless DominoThe first gate in the chain needs a foot switchPrecharge is rippling – short-circuit currentVDDClk MpOut1In11 0VDDClk MpOut2In2VDDClk MpOutnInnIn31 00 1 0 1 0 11 0 1 0EE14114EECS14114Lecture #21Footless DominoFootless DominoCan mitigate short-circuit current by alternating between footed and unfooted dominoEE14115EECS14115Lecture #21Footless DominoFootless DominoTo eliminate the short-circuit current, can delay the clock for each stageVDDClk MpOut1In11 0VDDClk MpOut2In2VDDClk MpOutnInnIn31 00 1 0 1 0 11 0 1 0EE14116EECS14116Lecture #21Differential (Dual Rail) DominoDifferential (Dual Rail) DominoABMeMpClkClkOut = AB!A !BMkpClkOut = ABMkpMpAllows inverting gates to be builtEE14117EECS14117Lecture #21npnp--CMOSCMOSIn1In2PDNIn3MeMpClkClkOut1In4PUNIn5MeMpClkClkOut2(to PDN)1 → 11 → 00 → 00 → 1Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUNEE14118EECS14118Lecture #21NORA LogicNORA LogicIn1In2PDNIn3MeMpClkClkOut1In4PUNIn5MeMpClkClkOut2(to PDN)1 → 11 → 00 → 00 → 1Fast, but EXTREMELY sensitive to noise!EE14119EECS14119Lecture #21Next LectureNext Lecture Flops and


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Berkeley ELENG 141 - Lecture 21 Domino Logic

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