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Berkeley ELENG 141 - Lecture Notes

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EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 13Lecture 13CMOS logicCMOS logicDesign for speedDesign for speedEE1412EECS141AnnouncementsAnnouncements Hardware lab this week Lab 4 due this week Homework #6 due next TuesdayEE1413EECS141Class MaterialClass Material Last lecture CMOS logic gates Today’s lecture Design for speed Reading (Chapter 6)EE1414EECS141Static CMOS Static CMOS DesignDesignEE1415EECS141Switch Delay ModelSwitch Delay ModelAReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintEE1416EECS141Input Pattern Effects on DelayInput Pattern Effects on Delay Delay is dependent on the pattern of inputs Low to high transition both inputs go low– delay is 0.69 Rp/2 CL one input goes low– delay is 0.69 RpCL High to low transition both inputs go high– delay is 0.69 2RnCLCLBRnARpBRpARnCintEE1412EE1417EECS141Delay Dependence on Input PatternsDelay Dependence on Input Patterns-0.500.511.522.530 100 200 300 400A=B=1→0A=1, B=1→0A=1 →0, B=1time [ps]Voltage [V]81A= 1→0, B=180A=1, B=1→045A=B=1→061A= 0→1, B=164A=1, B=0→167A=B=0→1Delay(psec)Input DataPatternNMOS = 0.5μm/0.25 μmPMOS = 0.75μm/0.25 μmCL= 100 fFEE1418EECS141Transistor SizingTransistor SizingCLBRnARpBRpARnCintBRpARpARnBRnCLCint22221144EE1419EECS141Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS GateOUT = D + A • (B + C)DABCDABC12224488EE14110EECS141Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS GateOUT = D + A • (B + C)DABCDABC12226366EE14111EECS141FanFan--In ConsiderationsIn ConsiderationsDCBADCBACLC3C2C1Distributed RC model(Elmore delay)tpHL= 0.69 Reqn(C1+2C2+3C3+4CL)Propagation delay deteriorates rapidly as a function of fan-in –quadratically in the worst case.EE14112EECS141ttppas a Function of Fanas a Function of Fan--InIntpLHtp(psec)fan-inGates with a fan-in greater than 4 should be avoided.025050075010001250246810121416tpHLquadraticlineartpEE1413EE14113EECS141ttppas a Function of Fanas a Function of Fan--OutOut246810121416tpNOR2tp(psec)eff. fan-out = CL/CinAll gates have the same drive current.tpNAND2tpINVSlope is a function of “driving strength”EE14114EECS141ttppas a Function of Fanas a Function of Fan--In and FanIn and Fan--OutOut Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CLtp= a1FI + a2FI2+ a3FOEE14115EECS141Fast Complex Gates:Fast Complex Gates:Design Technique 1Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizingInNCLC3C2C1In1In2In3M1M2M3MNDistributed RC lineM1 > M2 > M3 > … > MN(the FET closest to theoutput is the smallest)Can reduce delay by more than 20%; Be careful: input loading, junction caps, decreasing gains as technology shrinksEE14116EECS141Fast Complex Gates:Fast Complex Gates:Design Technique 2Design Technique 2 Transistor orderingC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical path critical pathcharged10→1chargedcharged1delay determined by time to discharge CL, C1and C2delay determined by time to discharge CL110→1chargeddischargeddischargedEE14117EECS141Fast Complex Gates:Fast Complex Gates:Design Technique 3Design Technique 3 Alternate logic structuresF = ABCDEFGHEE14118EECS141Fast Complex Gates:Fast Complex Gates:Design Technique 4Design Technique 4 Isolating fan-in from fan-out using buffer insertionCLCLEE1414EE14119EECS141Fast Complex Gates:Fast Complex Gates:Design Technique 5Design Technique 5 Reducing the voltage swing linear reduction in delay also reduces power consumption But the following gate is much slower! Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design)tpHL= 0.69 (3/4 (CL VDD)/ IDSATn)= 0.69 (3/4 (CL Vswing)/ IDSATn)EE14120EECS141Logical Logical EffortEffortEE14121EECS141Buffer ExampleBuffer Example()∑=+=NiifDelay11For given N: Ci+1/Ci= Ci/Ci-1To find N: Ci+1/Ci~ 4How to generalize this to any logic path?CL = CN+1In Out12 N(in units of τinv)fi= Ci+1/CiC1C2CNEE14122EECS141Logical EffortLogical Effort()fgpCCCRkDelayinLunitunit⋅+=⎟⎟⎠⎞⎜⎜⎝⎛+⋅=τγ1p – intrinsic delay (3kRunitCunitγ) - gate parameter ≠ f(W)g – logical effort (kRunitCunit) – gate parameter ≠ f(W)f – electrical effort (effective fanout)Normalize everything to an inverter:ginv=1, pinv= 1Divide everything by τinv(everything is measured in unit delays τinv)Assume γ = 1.EE14123EECS141Delay in a Logic GateDelay in a Logic GateGate delay:d = h + peffort delayintrinsic delayEffort delay:h = g flogical efforteffective fanout = Cout/CinLogical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate sizeEE14124EECS141Logical EffortLogical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexityEE1415EE14125EECS141Logical EffortLogical EffortLogical effort is the ratio of input capacitance of a gate (input) to the input capacitance of an inverter with the same output currentg = 1g = 4/3g = 5/3BAABFVDDVDDABABFVDDAAF1222221144Inverter 2-input NAND 2-input NOREE14126EECS141Logical Effort of GatesLogical Effort of GatesFan-out (f)Normalized delay (d)t1 2 3 4 5 6 7 pINVtpNANDF(Fan-in)g=p=d=g=p=d=EE14127EECS141Logical Effort of GatesLogical Effort of GatesFan-out (f)Normalized delay (d)t1 2 3 4 5 6 7 pINVtpNANDF(Fan-in)g=1p=1d=h+1g=4/3p=2d=(4/3)h+2EE14128EECS141Logical Effort of GatesLogical Effort of GatesIntrinsicDelayEffortDelay12345Fanout f12345Inverter:g = 1;p = 12-input NAND:g = 4/3;p = 2Normalized DelayEE14129EECS141Add Branching EffortAdd Branching EffortBranching effort: pathonpathoffpathonCCCb−−−+=Coff-pathCon-pathEE14130EECS141Multistage NetworksMultistage NetworksStage effort: hi= gifiPath electrical effort: F = Cout/CinPath logical effort: G = g1g2…gNBranching effort: B = b1b2…bNPath effort: H = GFBPath delay D = Σdi= Σpi+ Σhi()∑=⋅+=NiiiifgpDelay1EE1416EE14131EECS141Optimum Effort per StageOptimum Effort per StageHhN=When each stage bears the same effort:NHh =()PNHpfgDNiii+=+=∑/1ˆMinimum path delayEffective fanout of each stage:iighf =Stage efforts: g1f1= g2f2=


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Berkeley ELENG 141 - Lecture Notes

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