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Berkeley ELENG 141 - Dynamic Logic

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EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 19Lecture 19Dynamic LogicDynamic LogicEE1412EECS141AnnouncementsAnnouncements No new homework this week Project phase two in lab next week Midterm 2 on Thursday, 6:30-8pm, 50 Birge Review session tonight 6-7:30 in 60 Evans No lecture on ThursdayEE1412EE1413EECS141EE1414EECS141Class MaterialClass Material Last lecture Pass-transistor logic Today’s lecture Dynamic logic Domino logic Reading Chapter 6EE1413EE1415EECS141Dynamic LogicDynamic LogicEE1416EECS141Dynamic CMOSDynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDDvia a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistorsEE1414EE1417EECS141Dynamic GateDynamic GateIn1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMeTwo phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)EE1418EECS141Dynamic GateDynamic GateIn1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMeTwo phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)onoff1offon((AB)+C)EE1415EE1419EECS141Conditions on OutputConditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CLEE14110EECS141Properties of Dynamic GatesProperties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL= GND and VOH= VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CLEE1416EE14111EECS141Properties of Dynamic GatesProperties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDDand GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIHand VILequal to VTn low noise margin (NML) Needs a precharge/evaluate clockEE14112EECS141Issues in Dynamic Design 1: Issues in Dynamic Design 1: Charge LeakageCharge LeakageCLClkClkOutAMpMeLeakage sourcesCLKVOutPrechargeEvaluateDominant component is subthreshold currentEE1417EE14113EECS141Solution to Charge LeakageSolution to Charge LeakageCLClkClkMeMpABOutMkpSame approach as level restorer for pass-transistor logicKeeperEE14114EECS141Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge SharingCLClkClkCACBB=0AOutMpMeCharge stored originally on CLis redistributed (shared) over CLand CAleading to reduced robustnessEE1418EE14115EECS141Charge Sharing ExampleCharge Sharing ExampleCL=50fFClkClkAABBB!BCCOutCa=15fFCc=15fFCb=15fFCd=10fFEE14116EECS141Charge SharingCharge SharingCLVDDCLVoutt()CaVDDVTnVX()–()+=orΔVoutVoutt()VDD–CaCL--------VDDVTnVX()–()–==ΔVoutVDDCaCaCL+----------------------⎝⎠⎜⎟⎛⎞–=case 1) if ΔVout < VTncase 2) if ΔVout > VTnB=0ClkXCLCaCbAOutMpMaVDDMbClkMeEE1419EE14117EECS141Solution to Charge RedistributionSolution to Charge RedistributionClkClkMeMpABOutMkpClkPrecharge internal nodes using a clock-driven transistor (at the cost of increased area and power)EE14118EECS141Issues in Dynamic Design 3: Issues in Dynamic Design 3: BackgateBackgateCouplingCouplingCL1ClkClkB=0A=0Out1MpMeOut2CL2InDynamic NAND Static NAND=1=0EE14110EE14119EECS141BackgateBackgateCoupling EffectCoupling Effect-101230246VoltageTime, nsClkInOut1Out2EE14120EECS141Issues in Dynamic Design 4: Clock Issues in Dynamic Design 4: Clock FeedthroughFeedthroughCLClkClkBAOutMpMeCoupling between Out and Clk input of the prechargedevice due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.EE14111EE14121EECS141Clock Clock FeedthroughFeedthrough-0.50.51.52.500.51ClkClkIn1In2In3In4OutIn &ClkOutTime, nsVoltageClock feedthroughClock feedthroughEE14122EECS141EE14112EE14123EECS141Other EffectsOther Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)EE14124EECS141Domino LogicDomino LogicEE14113EE14125EECS141Cascading Dynamic GatesCascading Dynamic GatesClkClkOut1InMpMeMpMeClkClkOut2VtClkInOut1Out2ΔVVTnOnly 0 → 1 transitions allowed at inputs!EE14126EECS141Domino LogicDomino LogicIn1In2PDNIn3MeMpClkClkOut1In4PDNIn5MeMpClkClkOut2Mkp1 → 11 → 00 → 00 → 1EE14114EE14127EECS141Why Domino?Why Domino?ClkClkIniPDNInjIniInjPDNIniPDNInjIniPDNInjLike falling


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Berkeley ELENG 141 - Dynamic Logic

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