EE1411EECS1411Lecture #19EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 19Lecture 19Dynamic LogicDynamic LogicEE1412EECS1412Lecture #19AnnouncementsAnnouncements Next Tues. lecture may be taped ahead (earlier in the morning) Please look out for announcement on website. Midterm 2: Thurs. Nov. 5th, 6:30-8:00pm Includes all material up to and including Lecture 18 Exam starts at 6:30pm sharp Review session: Wed., Nov. 4th, 6:00-7:00pm, room TBD Project phase 2 out next Thurs., due following Fri. One extra day because of holiday Yue’s office hours moved to 353 CoryEE1413EECS1413Lecture #19Class MaterialClass Material Last lecture Ratioed and Pass-Transistor Logic Today’s lecture Dynamic logic Reading Chapter 6EE1414EECS1414Lecture #19Dynamic LogicDynamic LogicEE1415EECS1415Lecture #19Dynamic CMOSDynamic CMOS In static circuits, at every point in time (except when switching) the output is connected to either GND or VDDvia a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. only requires n + 2 (n+1 N-type + 1 P-type) transistorsEE1416EECS1416Lecture #19Dynamic GateDynamic GateIn1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMeTwo phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)onoff1offon((AB)+C)EE1417EECS1417Lecture #19Conditions on OutputConditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CLEE1418EECS1418Lecture #19Properties of Dynamic GatesProperties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL= GND and VOH= VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced capacitance due to lower input capacitance (Cin) no Isc, so all the current provided by PDN goes into discharging CLEE1419EECS1419Lecture #19LE of Dynamic GatesLE of Dynamic GatesInClkClkOutCLCgate=LE = AClkClkOutCLBCgate=LE = EE14110EECS14110Lecture #19Power Consumption of Dynamic GatesPower Consumption of Dynamic GatesIn1In2PDNIn3MeMpCLKCLKOutCLPower only dissipated when previous Out = 0EE14111EECS14111Lecture #19Dynamic Power Consumption is Dynamic Power Consumption is Data DependentData Dependent011001010100OutBADynamic 2-input NOR GateAssume signal probabilitiesPA=1 = 1/2PB=1 = 1/2Then transition probabilityP0→1 = Pout=0 x Pout=1= 3/4 x 1 = 3/4Switching activity always higher in dynamic gates!P0→1 = Pout=0EE14112EECS14112Lecture #19Properties of Dynamic GatesProperties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDDand GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIHand VILequal to VTn low noise margin (NML) Needs a precharge/evaluate clockEE14113EECS14113Lecture #19Issues in Dynamic Design 1: Issues in Dynamic Design 1: Charge LeakageCharge LeakageCLClkClkOutAMpMeLeakage sourcesCLKVOutPrechargeEvaluateDominant component is subthreshold currentEE14114EECS14114Lecture #19Solution to Charge LeakageSolution to Charge LeakageCLClkClkMeMpABOutMkpSame approach as level restorer for pass-transistor logicKeeperEE14115EECS14115Lecture #19Dynamic Gate VTCDynamic Gate VTCCLClkClkMeMpAOutMkpOutEE14116EECS14116Lecture #19Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge SharingCLClkClkCACBB=0AOutMpMe Charge initially stored on CL CApreviously discharged When A rises, this charge is redistributed (shared) between CLand CA Makes Out drop below VDDEE14117EECS14117Lecture #19Charge Sharing ExampleCharge Sharing ExampleEE14118EECS14118Lecture #19Charge SharingCharge SharingB=0ClkXCLCaCbAOutMpMaVDDMbClkMe• Two cases:•Mastays on – complete charge share•Maturns off – incomplete charge share•Complete charge share:•QCa= VOutCa∆QCL= -VOutCaÆ ∆VOut= -VDDCa/(Ca+CL)•Incomplete charge share:•QCa= (VDD-VTN*)Ca∆QCL= -(VDD-VTN*)CaÆ ∆VOut= -(VDD-VTN*)Ca/CLEE14119EECS14119Lecture #19Solution to Charge SharingSolution to Charge SharingClkClkMeMpABOutMkpClk• Keeper helps a lot• Can still get failures if Out drops below inverter Vsw• Another option: precharge internal nodes• Increases power and areaEE14120EECS14120Lecture #19Issues in Dynamic Design 3: Clock Issues in Dynamic Design 3: Clock FeedthroughFeedthroughCLClkClkBAOutMpMeCoupling between Out and Clk input of the prechargedevice due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.EE14121EECS14121Lecture #19Clock Clock FeedthroughFeedthrough-0.50.51.52.500.51ClkClkIn1In2In3In4OutIn &ClkOutTime, nsVoltageClock feedthroughClock feedthroughEE14122EECS14122Lecture #19Other EffectsOther Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)EE14123EECS14123Lecture #19Next LectureNext Lecture Domino
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