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Berkeley ELENG 141 - LE and Power for Decoders

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EE1411EECS1411Lecture #8EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 8Lecture 8LE and Power for DecodersLE and Power for DecodersEE1412EECS1412Lecture #8AnnouncementsAnnouncements Lab #3 Mon. and Tues., Lab #4 Fri. Homework #4 due ThursdayEE1413EECS1413Lecture #8Class MaterialClass Material Last lecture Gate delay and logical effort Today’s lecture Logical effort and power in decoders Reading (Chapter 6)EE1414EECS1414Lecture #8DecodersDecodersEE1415EECS1415Lecture #8Decoder Design ExampleDecoder Design Example Look at decoder for 256x256 memory block (8KBytes) EE1416EECS1416Lecture #8Problem SetupProblem Setup Goal: Build fastest possible decoder with static CMOS logic What we know Basically need 256 AND gates, each one of them drives one word lineN=8EE1417EECS1417Lecture #8Problem Setup (1)Problem Setup (1) Each word line has 256 cells connected to it CWL= 256*Ccell+ Cwire Ignore wire for now (include it later in the class)EE1418EECS1418Lecture #8Problem Setup (2)Problem Setup (2) Assume that decoder input capacitance is Caddress=4*CcellEE1419EECS1419Lecture #8Problem Setup (3)Problem Setup (3) Each address drives 28/2 AND gates A0 drives ½ of the gates, A0_b the other ½ of the gatesEE14110EECS14110Lecture #8Problem Setup (4)Problem Setup (4) Total fanout on each address wire is: ()()871322256128 2 242cellcellloadin cell cellCCCFBCC C=Π = = =EE14111EECS14111Lecture #8Decoder FanDecoder Fan--OutOut F of 213means that we will want to use more than log4(213) = 6.5 stages to implement the AND8 Need many stages anyways So what is the best way to implement the AND gate? Will see next that it’s the one with the most stages and least complicated gatesEE14112EECS14112Lecture #888--Input ANDInput ANDLE=10/3 1 ΠLE = 10/3P = 8 + 1LE=2 5/3ΠLE = 10/3P = 4 + 2 LE=4/3 5/3 4/3 1ΠLE = 80/27P = 2 + 2 + 2 + 1EE14113EECS14113Lecture #888--Input ANDInput AND Using 2-input NAND gates 8-input gate takes 6 stages Total LE is (4/3)3≈ 2.4 So PE is 2.4*213– optimal N of ~7.1EE14114EECS14114Lecture #8Decoder So FarDecoder So Far 256 8-input AND gates Each built out of tree of NAND gatesand inverters Issue: Every address line hasto drive 128 gates (andwire) right away Can’t build gates small enough - Forces us to add buffers just to drive address inputsEE14115EECS14115Lecture #8Look Inside Each AND8 GateLook Inside Each AND8 GateEE14116EECS14116Lecture #8PredecodersPredecoders Use a single gate for each of the shared terms E.g., from A0, A0, A1, and A1, generate four signals: A0A1, A0A1, A0A1, A0A1 In other words, we are decoding smaller groups of address bits first And using the “predecoded” outputs to do the rest of the decodingEE14117EECS14117Lecture #8Predecoder and DecoderPredecoder and DecoderA0 A1A4 A5A2 A3EE14118EECS14118Lecture #8PredecoderPredecoder/Decoder Layout/Decoder LayoutEE14119EECS14119Lecture #8PredecodePredecodeOptionsOptions Two options for predecoding:EE14120EECS14120Lecture #8PredecodePredecodeOptions (2)Options (2) Larger predecode usually better: More stages before the long wires Decreases their effect on the circuit Fewer long wires switch Lower power Easier to fit 2-input gate into cell pitchCL1161162564 to 16 predecoderA0 A1 A2A3A0A1A2A3EE14121EECS14121Lecture #8What We Now KnowWhat We Now Know Given decoder structure, input capacitance, final load Can size the entire chain using LE for minimum delay Is this the “best” we can do in terms of power too? Not necessarily – probably want to reduce sizes – (especially on final decoder inputs) Is there anything else we can do to improve energy even further?EE14122EECS14122Lecture #8PowerPower If we lower the supply voltage, energy from switching capacitors drops quadratically! But, how does this impact delay?  Need to look more closely at transistor behavior…210 DDLVCE =→iLVinVoutCLVDDEE14123EECS14123Lecture #8Next LectureNext Lecture MOS transistor


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Berkeley ELENG 141 - LE and Power for Decoders

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