UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on October 15, 2006. Borivoje Nikolić FALL 2006 TERM PROJECT PHASE I EECS 141 1. Design of a 32x16-bit 3R 2W register file – Background Memory arrays are an essential building block of all digital systems. In this semester’s project, we will design a register file that consists of 32 16-bit words. 1.1. High level structure A block diagram of the register file is shown in Figure 1. Figure 1. SRAM array block diagram. There are two major parts to be designed: • Address decoder: The address decoder takes in 5 address lines, (provided only as true values) a4-a0 and produces 32x5 select signals wl31a-wl0e. Indices a-e corresponds to write and read ports in the registers, where a and b are write ports and c-e are read ports. Control signals select the write port within each register. When all control signals are low, all wordlines are 0. • Register array: Consists of an array of 32 x 16 3-read 2-write registers. In addition to these blocks the array also has a circuitry that allows writing the data and precharging the bitlines to VDD before the read operation, which is not shown in figure.2. Implementation and Constraints The goal of this project is to design a functional, compact and fast single-ended register file for use in high-performance or mobile microprocessor with a particular set of optimization criteria. The project will be completed in THREE phases. PHASE 1, due Monday, October 30, at 10am. In the first phase of the project, you will design a cell for the register file that allows 2 write ports and 3 simultaneous reads. The goal is to design a stable and fast cell with minimum size, suitable for single-ended operation. The cell layout should have straight stripes of diffusion and poly, and should not exceed the width of 8 metal-5 tracks in the datapath direction (Note, cell width is specified, and the height should be minimized). With minimized cell size, the second goal is to get the largest read current. To guarantee functionality, the cell should be sized to prevent the voltage rise higher than 0.4V at the storage node during the read operation (the bitlines are precharged to VDD before the read operation). The cell writeability must be guaranteed as well. You will have to report the read and write margins for the cell. Prelab: hand design of the register cell: schematic and a stick diagram. PHASE 2, due Monday, November 13, at 10am. Design of the 5-to-32 memory decoder. The input loading of each of the true and complementary address lines is constrained to be less than 5fF. The output loading of the decoder is determined from the wordline loading of the register file and the wireload. The length of the wordline can be determined from the horizontal dimension of the cell. The decoding is performed in two phases: predecoding and the final row decoding of 2 bits. The predecoder drives the final decoders together with the wire that whose length equals the height of the memory array. Prelab: hand design of the decoder, using the method of logical effort. The complete decoder in schematic and layout should be done in Cadence. Note that decoder pitch in layout has to match the register file pitch. PHASE 3, due Monday, November 20, at 10am. Assemble the complete array and simulate its performance. PROJECT POSTERS, Tuesday, November 21, 11-12:30pm. In each phase of the design you will turn in a short report. A longer report, together with a poster presentation is due on November 21.Physical and electrical specifications: 2.1. TECHNOLOGY: The design is to be implemented in a 0.25 μm CMOS process with 5 metal layers. You should use only up to 4 metal layers for the register file design. The SPICE technology is in the g25.mod file. 2.2. POWER SUPPLY: You are free to choose any supply voltage and logic swing up to 2.5 V. Make sure that you use the appropriate model when you perform any hand analysis. 2.3. PERFORMANCE METRIC: The propagation delay for static CMOS design is defined as the time interval between the 50% transition point of the inputs and the 50% point of the worst-case output signal. Make sure you pick the worst-case condition and state EXPLICITLY in your report what that condition is! Note that the delay definitions might be different for the sense-amplifiers. 2.4. AREA: The area is defined as the smallest rectangular box that can be drawn around the design. Since the register file must interface with the rest of the chip, all inputs and outputs must be accessible from the boundary of the block. 2.5. NAMING CONVENTIONS: The input operands of the memory are named a<4:0>. The output data is d<15:0>. Wordline and bitline signals are labeled as wlx<31:0> (where ‘x’ corresponds to the appropriate read or write port) and bl1r<15:0>, bl3r<15:0>, bl3r<15:0>, bl1w<15:0>, bl2w<15:0>. 2.6. REGISTERS: You don’t need to use any registers in this design. 2.7. CLOCKS: You will need at most one clock for the precharge of bitlines. Remember that the load capacitance of the clock should be included in the energy analysis. 2.8. VOH, VOL, NOISE MARGINS: You are free to choose your logic swing in the decoder. The noise margins should be at least 10% of the supply voltage. 2.9. RISE AND FALL TIMES: All input signals have rise and fall times of 50 ps. The rise and fall times of the output signals (10% to 90%) should not exceed 200ps (unless otherwise noted). 2.10. LOAD CAPACITANCE: Your output is driving a 20fF load at each output. 2.11. INPUT CAPACITANCE: Each address input should not load the previous stage with more than 3fF (less is OK). The goal is to minimize the area of a functional array. Delay and power should also be minimized.3. Simulation Analyze the circuit by hand. Also use HSPICE to simulate the design and prove that it functions correctly. You will need to determine the input pattern that causes the worst-case propagation delay or energy consumption by analyzing your circuit schematic. 4. Report The quality of your report is as important as the quality of your design. Be sure to provide all relevant information and eliminate unnecessary material. Organization, conciseness, and completeness are of paramount importance. Do not repeat information we already know. Use the templates provided on the web page (Word and PDF formats). Make sure to fill in the cover-page
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