EE141-Spring 2008 Digital Integrated CircuitsAnnouncementsSlide Number 3ReviewStick DiagramsTwo Versions of C • (A + B)Logic GraphsConsistent Euler PathOAI22 Logic GraphExample: x = ab+cdMulti-Fingered TransistorsCMOS PropertiesSlide Number 13Review: Transistor Switch ModelSwitch Delay ModelInput Pattern Effects on DelayDelay Dependence on Input PatternDelay Dependence on Input PatternDelay Dependence on Input PatternTransistor SizingTransistor Sizing a Complex CMOS GateNote on Transistor SizingFan-In ConsiderationsFan-In Considerationstp as a Function of Fan-Intp as a Function of Fan-Outtp as a Function of Fan-In and Fan-OutFast Complex Gates: Design Technique 1Fast Complex Gates: Design Technique 2Fast Complex Gates: Design Technique 3Fast Complex Gates: Design Technique 4Fast Complex Gates: Design Technique 5EE141EECS1411Lecture #12EE141EE141--Spring 2008Spring 2008 Digital Integrated Digital Integrated CircuitsCircuitsLecture Lecture 1212CMOS CMOS LogicLogic--speedspeedEE141EECS1412Lecture #12AnnouncementsAnnouncements Lab5 this week Midterm results next WeEE141EECS1413Lecture #12CMOS LogicCMOS LogicEE141EECS1414Lecture #12ReviewReview Last lecture: CMOS Logic Standard cell design This lecture Performance optimization in CMOS logicEE141EECS1415Lecture #125Stick DiagramsStick DiagramsContains no dimensionsRepresents relative positions of transistorsInOutVDDGNDInverterAOutVDDGNDBNAND2EE141EECS1416Lecture #12Two Versions of C Two Versions of C •• (A + B)(A + B)XCA B A B CXVDDGNDVDDGNDEE141EECS1417Lecture #12Logic GraphsLogic GraphsCA BX = C • (A + B)BACijVDDXXiGNDABCPUNPDNABCLogic GraphjEE141EECS1418Lecture #12Consistent Euler PathConsistent Euler PathjVDDXXiGNDABCA B CHas PDN and PUNABCHas PUN, but no PDNEE141EECS1419Lecture #12OAI22 Logic GraphOAI22 Logic GraphCA BX = (A+B)•(C+D)BADVDDXXGNDABCPUNPDNCDDABCDEE141EECS14110Lecture #12Example: x = ab+cdExample: x = ab+cdGNDxabcdVDDxGNDxabcdVDDx(a) Logic graphs for (ab+cd)(b) Euler Paths {a b c d}acdxVDDGND(c) stick diagram for ordering {a b c d}bEE141EECS14111Lecture #12MultiMulti--Fingered TransistorsFingered TransistorsOne fingerTwo fingers (folded)Less diffusion capacitanceEE141EECS14112Lecture #12CMOS PropertiesCMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistorsEE141EECS14113Lecture #12Static CMOS Static CMOS DesignDesignEE141EECS14114Lecture #12Review: Transistor Switch ModelReview: Transistor Switch ModelGS TVV>EE141EECS14115Lecture #12Switch Delay ModelSwitch Delay ModelAReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintEE141EECS14116Lecture #12Input Pattern Effects on DelayInput Pattern Effects on Delay Delay is dependent on thepattern of inputs Both R and C vary with input pattern Low to high transition both inputs go low– Resistance is Rp /2 one input goes low– Resistance os Rp High to low transition both inputs go high– Resistance is 2RnCLBRnARpBRpARnCintEE141EECS14117Lecture #12Delay Dependence on Input PatternDelay Dependence on Input Pattern Use RC model to estimate delayEE141EECS14118Lecture #12Delay Dependence on Input PatternDelay Dependence on Input Pattern Use RC model to estimate delayEE141EECS14119Lecture #12Delay Dependence on Input PatternDelay Dependence on Input Pattern Use RC model to estimate delayEE141EECS14120Lecture #12Transistor SizingTransistor SizingCLBRnARpBRpARnCintBRpARpARnBRnCLCint222 21144EE141EECS14121Lecture #12Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS GateOUT = D + A • (B + C)DAB CDABC122 26366EE141EECS14122Lecture #12Note on Transistor SizingNote on Transistor Sizing So far, we have assumed that MOSFETsbehave like linear resistor when we put two of them in series I.e., IDSATof stack of 2 transistors = ½ IDSATof single transistor With velocity saturated devices, this is not the case More in future homeworksEE141EECS14123Lecture #12FanFan--In ConsiderationsIn ConsiderationsDCBAD: 0Æ1C: 1B: 1A: 1CLC3C2C1RC model:2 2224444EE141EECS14124Lecture #12FanFan--In ConsiderationsIn ConsiderationsDCBADCBACLC3C2C1Distributed RC model(Elmore delay)tpHL = 0.69 Reqn (C1 +2C2 +3C3 +4CL )Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.2 2224444EE141EECS14125Lecture #12ttpp as a Function of Fanas a Function of Fan--InIntp(psec)fan-inGates with a fan-in greater than 4 should be avoided.tpHLquadraticlineartptpLHEE141EECS14126Lecture #12ttpp as a Function of Fanas a Function of Fan--OutOuttp NOR2tp(psec)eff. fan-out = CL /CinAll gates have the same drive current.tp NAND2tp INVSlope is a function of “driving strength”EE141EECS14127Lecture #12ttpp as a Function of Fanas a Function of Fan--In and FanIn and Fan--OutOut Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CLtp = a1 FI + a2 FI2 + a3 FOEE141EECS14128Lecture #12Fast Complex Gates:Fast Complex Gates: Design Technique 1Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizingInNCLC3C2C1In1In2In3M1M2M3MNDistributed RC lineM1 > M2 > M3 > … > MN(the FET closest to theoutput is the smallest)Can reduce delay by more than 20%; Be careful: input loading, junction caps, decreasing gains as technology shrinksEE141EECS14129Lecture #12Fast Complex Gates:Fast Complex Gates: Design Technique 2Design Technique 2 Transistor orderingC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical path critical pathcharged10→1chargedcharged1delay determined by time to discharge CL , C1 and C2delay determined by time to discharge CL110→1chargeddischargeddischargedEE141EECS14130Lecture #12Fast Complex Gates:Fast Complex Gates: Design Technique 3Design Technique 3 Alternate logic structuresF = ABCDEFGHEE141EECS14131Lecture #12Fast Complex Gates:Fast Complex Gates: Design Technique 4Design Technique 4 Isolating fan-in from fan-out using buffer insertionCLCLEE141EECS14132Lecture #12Fast Complex Gates:Fast Complex Gates: Design Technique 5Design Technique 5 Reducing the voltage swing linear
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