EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 29Lecture 29ROM, Flash, DRAMROM, Flash, DRAMEE1412EECS141AnnouncementsAnnouncements Homework 10 due today Will post all grades on Monday or Tuesday Please check them Extra office hours Prof. Nikolic M 10:30-12am Review session on Monday afternoonEE1413EECS141Class MaterialClass Material Last lecture Adders, Multipliers Today’s lecture ROM Flash DRAM Reading Chapter 12EE1414EECS141Other Types of Other Types of MemoryMemoryEE1415EECS141Semiconductor Memory ClassificationSemiconductor Memory ClassificationRead-Write MemoryNon-VolatileRead-WriteMemoryRead-Only MemoryEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFOEE1416EECS141ReadRead--Only Memory CellsOnly Memory CellsWLBLWLBL1WLBLWLBLWLBL0VDDWLBLGNDDiode ROM MOS ROM 1 MOS ROM 2EE1412EE1417EECS141MOS OR ROMMOS OR ROMWL[0]VDDBL[0]WL[1]WL[2]WL[3]VbiasBL[1]Pull-down loadsBL[2] BL[3]VDDEE1418EECS141MOS NOR ROMMOS NOR ROMWL[0]GNDBL[0]WL[1]WL[2]WL[3]VDDBL[1]Pull-up devicesBL[2] BL[3]GNDEE1419EECS141MOS NOR ROM LayoutMOS NOR ROM LayoutProgrammming using theActive Layer OnlyPolysiliconMetal1DiffusionMetal1 on DiffusionCell (9.5λ x 7λ)EE14110EECS141MOS NOR ROM LayoutMOS NOR ROM LayoutPolysiliconMetal1DiffusionMetal1 on DiffusionCell (11λ x 7λ)Programmming usingthe Contact Layer OnlyEE14111EECS141MOS NAND ROMMOS NAND ROMAll word lines high by default with exception of selected rowWL[0]WL[1]WL[2]WL[3]VDDPull-up devicesBL[3]BL[2]BL[1]BL[0]EE14112EECS141MOS NAND ROM LayoutMOS NAND ROM LayoutNo contact to VDD or GND necessary;Loss in performance compared to NOR ROMdrastically reduced cell sizePolysiliconDiffusionMetal1 on DiffusionCell (8λ x 7λ)Programmming usingthe Metal-1 Layer OnlyEE1413EE14113EECS141NAND ROM LayoutNAND ROM LayoutCell (5λ x 6λ)PolysiliconThreshold-alteringimplantMetal1 on DiffusionProgrammming usingImplants OnlyEE14114EECS141Flash EEPROMFlash EEPROMControl gateerasurep-substrateFloating gateThin tunneling oxiden⫹sourcen⫹drainprogrammingMany other options …EE14115EECS141A A ““ProgrammableProgrammable--ThresholdThreshold””TransistorTransistor“0”-state “1”-state⌬VTVWLVGS“ON”“OFF”IDEE14116EECS141FloatingFloating--Gate Transistor ProgrammingGate Transistor Programming0 V⫺5 V0 VDSRemoving programming voltage leaves charge trapped5 V⫺2.5 V5 VDSProgramming results inhigher VT.20 V10 V 5 V20 VDSAvalanche injectionEE14117EECS141CrossCross--sections of NVM cellssections of NVM cellsEPROMFlashCourtesy IntelEE14118EECS141Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――EraseEraseS D12 VGcell arrayBL0BL1open openWL0WL10 V0 V12 VEE1414EE14119EECS141Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――WriteWriteS D12 V6 VGBL0BL16 V 0 VWL0WL112 V0 V0 VEE14120EECS141Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――ReadRead5 V1 VGS DBL0BL11 V 0 VWL0WL15 V0 V0 VEE14121EECS141NAND Flash MemoryNAND Flash MemoryUnit CellWord line(poly)Source line(Diff. Layer)Courtesy ToshibaGateONOFGGateOxideEE14122EECS141NAND Flash MemoryNAND Flash MemoryWord linesSelect transistorBit line contact Source line contactActive areaSTICourtesy ToshibaEE14123EECS141DRAMDRAMEE14124EECS14111--Transistor DRAM CellTransistor DRAM CellWrite: CSis charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitanceVoltage swing is small; typically < 200 mV.M1CSWLBLCBLVDD⫺VTWLXsensingBLGNDWrite 1 Read 1VDDVDD/2 VDD/2ΔVBLVPRE–VBITVPRE–CSCSCBL+------------==VEE1415EE14125EECS141DRAM Cell ObservationsDRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDDEE14126EECS141Sense Amp OperationSense Amp Operation⌬V(1)V(1)V(0)tVPREVBLSense amp activatedWord line activatedEE14127EECS14111--T DRAM CellT DRAM CellUses Polysilicon-Diffusion CapacitanceExpensive in AreaM1wordlineDiffusedbit linePolysilicongatePolysiliconplateCapacitorCross-sectionLayoutMetal word linePolySiO2Field Oxiden+n+Inversion layerinduced byplate biasPolyEE14128EECS141Modern 1T DRAM CellsModern 1T DRAM CellsCell Plate SiCapacitor InsulatorStorage Node Poly2nd Field OxideRefilling PolySi SubstrateTrench CellStacked-capacitor CellCapacitor dielectric layerCell plateWord lineInsulating LayerIsolationTransfer gateStorage electrodeEE14129EECS141THE ENDTHE END This is just the
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