EE1411EECS1411Lecture #22EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 22Lecture 22Flops and LatchesFlops and LatchesEE1412EECS1412Lecture #22AnnouncementsAnnouncements Project phase 2 due Friday Phase 3 out this Friday Homework #8 out next Tues., due following Tues.EE1413EECS1413Lecture #22Sequential Elements:Sequential Elements:Flops and LatchesFlops and LatchesEE1414EECS1414Lecture #22Why Sequencing?Why Sequencing?EE1415EECS1415Lecture #22Sequential ElementsSequential Elements Latch – level sensitive Clk=0: “opaque” Clk-1: “transparent” Flip-flop – edge triggered Stores new data when ClkrisesDClkQDClkQClk ClkDDQQEE1416EECS1416Lecture #22Timing Definitions Timing Definitions --REVIEWREVIEWtCLKtDtc→qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQEE1417EECS1417Lecture #22Storage MechanismsStorage MechanismsDCLKCLKQStatic LatchDCLKCLKQDynamic LatchEE1418EECS1418Lecture #22Writing Into a Static LatchWriting Into a Static LatchCLKCLKCLKDQDCLKCLKQConverting into a MUX (gated feedback)Forcing the stateEE1419EECS1419Lecture #22MasterMaster--Slave FlipSlave Flip--Flop (EdgeFlop (Edge--Triggered Register)Triggered Register)10DCLKQMMaster01CLKQSlaveQMQDCLKTwo opposite latches create edge-triggered behaviorAlso called master-slave latch pair EE14110EECS14110Lecture #22MasterMaster--Slave RegisterSlave RegisterMultiplexer-based latch pairEE14111EECS14111Lecture #22Register Timing: Register Timing: ClkClk--Q DelayQ DelayDQCLK20.50.51.52.5tclk-q(LH)0.5 1 1.5 22.50time, nsecVoltstclk-q(HL)EE14112EECS14112Lecture #22Register Timing: Setup TimeRegister Timing: Setup TimeDQQMCLKI22 T22 0.5Volts0.00.2 0.4time (nsec)(a) Tsetup5 0.21 nsec0.6 0.8 100.51.01.52.02.53.0DQQMCLKI22 T22 0.5Volts0.00.2 0.4time (nsec)(b) Tsetup5 0.20 nsec0.6 0.8 100.51.01.52.02.53.0==EE14113EECS14113Lecture #22More Precise Setup TimeMore Precise Setup TimetD 2 CttttC 2 Q1.05tC 2 QtSutHClkDQ(a)tclk-q1.05(tclk-q)EE14114EECS14114Lecture #22Clk-Q DelayTSetup-1TClk-QTimeSetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)DCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1EE14115EECS14115Lecture #22Clk-Q DelayTSetup-1TClk-QTimeTimet=0ClockDataTSetup-1SetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)DCNQMCPD1SMInv1Inv2TG1EE14116EECS14116Lecture #22Clk-Q DelayTSetup-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1SetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)EE14117EECS14117Lecture #22Clk-Q DelayTSetup-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockDataTSetup-1SetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)EE14118EECS14118Lecture #22Timet=0ClockDataTSetup-1DCNQMCPD1SMInv1Inv2TG1SetupSetup--Hold Time IllustrationsHold Time IllustrationsCircuit before clock arrival (Setup-1 case)Clk-Q DelayTSetup-1TClk-QTimeEE14119EECS14119Lecture #22SetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 caseDCNQMCPD1SMInv1Inv2TG10Clk-Q DelayTHold-1TClk-QTimeEE14120EECS14120Lecture #22Clk-Q DelayTHold-1TClk-QTimeSetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 caseDCNQMCPD1SMInv1Inv2TG10EE14121EECS14121Lecture #22Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1SetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 case0EE14122EECS14122Lecture #22Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1SetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 case0EE14123EECS14123Lecture #22Clk-Q DelayTHold-1TClk-QTimeDCNQMCPD1SMInv1Inv2TG1Timet=0ClockTHold-1DataSetupSetup--Hold Time IllustrationsHold Time IllustrationsHold-1 case0EE14124EECS14124Lecture #22Other Latches/Registers: COther Latches/Registers: C22MOSMOSM1DQM3CLKM4M2CLKVDDCL1XCL2Master StageM5M7CLKCLKM8M6VDDSlave Stage*Usually includes feedback to staticizeEE14125EECS14125Lecture #22CC22MOS and Clock OverlapMOS and Clock OverlapEE14126EECS14126Lecture #22Other Latches/Registers: TSPCOther Latches/Registers: TSPCCLKInVDDCLKVDDInOutCLKVDDCLKVDDOutNegative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)EE14127EECS14127Lecture #22TSPC OperationTSPC OperationCLKInVDDCLKVDDIOutEE14128EECS14128Lecture #22Other Latches/Registers: Other Latches/Registers: PulsePulse--Triggered LatchesTriggered LatchesMaster-Slave LatchesDClkQ DClkQClkDataDClkQClkDataPulse-Triggered LatchL1 L2 LEE14129EECS14129Lecture #22Why not route the pulse?Why not route the pulse?EE14130EECS14130Lecture #22Next LectureNext Lecture
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