EE1411EECS1411Lecture #24EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 24Lecture 24Clock DistributionClock DistributionEE1412EECS1412Lecture #24AnnouncementsAnnouncements Homework #8 due today Project phase 3 Poster session Wed. Dec. 2rd@ BWRC Final report: Mon. Dec. 7th5:00pmEE1413EECS1413Lecture #24Class MaterialClass Material Last lecture Timing Today’s lecture Clock Distribution Reading Chapter 10EE1414EECS1414Lecture #24Layout Layout ParasiticsParasiticsEE1415EECS1415Lecture #24FloorplanningFloorplanningEE1416EECS1416Lecture #24Project Questions?Project Questions?EE1417EECS1417Lecture #24Clock Clock DistributionDistributionEE1418EECS1418Lecture #24Clock DistributionClock Distribution Single clock generally used to synchronize all logic on the same chip Need to distribute clock over the entire die While maintaining low skew/jitter (And without burning too much power)EE1419EECS1419Lecture #24Clock DistributionClock Distribution What’s wrong with just routing wires to every point that needs a clock?EE14110EECS14110Lecture #24HH--TreeTreeCLKEqual wire length/number of buffers to get to every locationEE14111EECS14111Lecture #24More realistic HMore realistic H--treetree[Restle98]EE14112EECS14112Lecture #24Clock GridClock GridDriverDriverDr ive rDr ive rGCLKGCLKGC LKGC LK•No RC matching•But huge powerEE14113EECS14113Lecture #24Example: DEC Alpha 21164 (1995)Example: DEC Alpha 21164 (1995) 2 phase single wire clock, distributed globally 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load, 20W power 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variationtrise= 0.35nstskew= 150pstcycle= 3.3nsClock waveformLocation of clockdriver on diepre-driverfinal driversEE14114EECS14114Lecture #24Clock DriversEE14115EECS14115Lecture #24Clock Skew in Alpha ProcessorClock Skew in Alpha ProcessorEE14116EECS14116Lecture #24 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width Local clocks can be gated “off” to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checkingtrise= 0.35ns tskew= 50pstcycle= 1.67nsEV6 (Alpha 21264) ClockingEV6 (Alpha 21264) Clocking600 MHz 600 MHz ––0.35 micron CMOS0.35 micron CMOSGlobal clock waveformPLLEE14117EECS14117Lecture #2421264 Clocking21264 ClockingEE14118EECS14118Lecture #24EV6 Clock ResultsEV6 Clock ResultsGCLK Skew(at Vdd/2 Crossings)ps5101520253035404550ps300305310315320325330335340345GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)EE14119EECS14119Lecture #24EV7 Clock Hierarchy (2002)EV7 Clock Hierarchy (2002)GCLK(CPU Core)L2L_CLK(L2 Cache)L2R_CLK(L2 Cache)NCLK(Mem Ctrl)DLLPLLSYSCLKDLLDLL+ widely dispersed drivers+ DLLs compensate static and low-frequency variation+ divides design and verification effort- DLL design and verification is added work+ tailored clocksActive Skew Management and Multiple Clock DomainsEE14120EECS14120Lecture #24Clock AnimationsClock Animations By Phillip Restle (IBM)http://www.research.ibm.com/people/r/restle/Animations/DAC01top.htmlEE14121EECS14121Lecture #24Next LectureNext Lecture Power distribution,
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