Jan M. Rabaey EE141 Term Project – Phase 2Specification EECS 141UNIVERSITY OF CALIFORNIACollege of EngineeringDepartment of Electrical Engineering and Computer SciencesLast modified on October 30, 2000 by Nathan Chan ([email protected])Jan M. Rabaey EE141 Term Project – Phase 2Specification EECS 141Due Tues., November 14th, 5pm @ 558 Coryor [email protected] Layout of Priority EncoderIn the second phase of the project, you are to realize a physical design of the priority encoder designed in phase 1. The design should be laid out using MAX, the layout editoryou should already be very familiar with. The version that you will be using is a significant improvement over previous releases because it allows for hierarchical extraction, which makes your SPICE decks a lot cleaner and easier to manage.Your layout must be free of design rule errors, and must include wells and sufficient contacts to all these wells. The latest version of MAX also provides easy generation of contacts, vias, and wells through the via g-cell normally located on the right subwindow of the layout editor. Each input, output, and appropriate supply rail should be brought to the edge of the pr-boundary with poly or any of the metal layers. As with any layout assignment, you will quickly discover that drawing layout is much simpler if you plan things out ahead of time. It is much easier to have a general layout strategy than to just blindly draw objects on the screen. For example, it is important to plan out how to distribute the supply and ground rails in your design. In addition, a design that is very regular can easily be tiled and reused, saving you a lot of time. MODULAR DESIGN WILL EARN YOU EXTRA CREDIT IN THIS PROJECT!Use common sense in laying out your circuit and remember that long transistors must be built properly. Consult your textbook if you don’t have a clue how to do this!Updating of ResultsMost probably, mapping your design into a physical implementation will probably cause some important changes in the energy and delay numbers. In addition, you must ensure that your layout and schematic are functionally equivalent (We call this LVS, by the way, for layout-versus-schematic). Hence, it is essential that you perform a full functional and performance analysis on the extracted circuit schematics. The goal of this phase of the project is to compare the results before and after physical design, not to improve on the design goals. Explain any major deviations from your results in Phase I. Try not to make any significant changes to your original design of Phase I. You may make minor modifications to the circuit that do not change the underlying principles that govern the circuit behavior of the design. If you find itabsolutely necessary to alter a major part of your circuit (because of non-functionality or unacceptable results), a full motivation should be provided in the report.Also, changes in the design goal are NOT allowed! ReportYour report for this phase of the project serves to accomplish two things: 1) You should discuss your overall layout strategy and how it is related to your original design goals. 2)Compare your results in this phase to those that you obtained in the first phase of the project, including any changes you made to the design.The total report should not contain more than two pages. You are NOT allowed to add any other sheets, except for important plots. Use the following guidelines to govern your report content and length: Page 1: Executive summary, overall design decisions, remarks, and motivations. Page 2: Layout of the stage with indication of the terminals.In addition to the report, you must electronically submit the extracted SPICE input deck used to obtain the energy analysis to [email protected]. Remember,the quality of the report is major factor in deciding your final project grade for this phase.Grading SchemePhase 2 is worth 20% of the total grade on the project. (Phase 1 is worth 40%, and Phase 3 is worth the remaining 40%) Your Phase 2 grade is divided evenly between your general approach and correctness (50%), and the quality of your report (50%).Frequently Asked QuestionsQ: Remember that automatic layout generator we used for the SUE lab…?A: Don’t even think about it. You must design the cell and its constituent sub-cells complete by hand. You will often find that the automatic layout generator does a lousy job. I’ll be very surprised if you get anything working with that.Q: Our design in Phase 1 was pretty fast, so I was wondering if I could switch from Power optimization to Speed optimization.A: No. You must stick with your original design goals. No exceptions.Q: My report is a little over 2 pages, and I would like to print EVERY single oneof my schematics so you can see the detail in my cells.A: Use some common sense. If it takes you more than two pages to explain everything, you must be doing a lousy job. As for the layout, just print the main cell as large as you can on the page. We really just want to see that your design isregular or has some structure. We can verify the “greatness” of the design when we run your decks through our
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