EE1411EE1411EE141Design Metrics EE141EE141--Spring 2004Spring 2004Lecture 3Lecture 3EE1412EE141Last LecturesLast Lectures Moore’s law Challenges in digital IC design in the next decade. Manufacturing processToday Design metricsEE1412EE1413EE141AdministriviaAdministrivia If you have not signed-in on the class roster, please do so after the lecture. Problems?EE1414EE141Design MetricsDesign Metrics How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a functionEE1413EE1415EE141Cost of Integrated CircuitsCost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip areaEE1416EE141NRE Cost is IncreasingNRE Cost is IncreasingEE1414EE1417EE141Die CostDie CostSingle dieWaferFrom http://www.amd.comGoing up to 12” (30cm)EE1418EE141G. Moore, ISSCC 2003EE1415EE1419EE141Cost per TransistorCost per Transistor0.00000010.00000010.0000010.0000010.000010.000010.00010.00010.0010.0010.010.010.10.1111982198219851985198819881991199119941994199719972000200020032003200620062009200920122012cost: cost: ¢¢--perper--transistortransistorFabrication capital cost per transistor (Moore’s law)EE14110EE141YieldYield%100per wafer chips ofnumber Totalper wafer chips good of No.×=Yyield Dieper wafer DiescostWafer cost Die×=()area die2diameterwafer area diediameter/2wafer per wafer Dies2××π−×π=EE1416EE14111EE141DefectsDefectsα−⎟⎠⎞⎜⎝⎛α×+=area dieareaunit per defects1yield dieα is approximately 3 4area) (die cost die f=EE14112EE141Some Examples (1994)Some Examples (1994)$4179%402961.5$15000.803Pentium$27213%482561.6$17000.703Super Sparc$14919%532341.2$15000.703DEC Alpha$7327%661961.0$13000.803HP PA 7100$5328%1151211.3$17000.804Power PC 601$1254%181811.0$12000.803486 DX2$471%360431.0$9000.902386DXDie costYieldDies/waferArea mm2Def./ cm2Wafer costLine widthMetal layersChipEE1417EE14113EE141ReliabilityReliability――Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuitsi(t)Inductive coupling Capacitive coupling Power and groundnoisev(t)VDDEE14114EE141DC OperationDC OperationVoltage Transfer CharacteristicVoltage Transfer CharacteristicV(x)V(y)VOHVOLVMVOHVOLfV(y)=V(x)Switching ThresholdNominal Voltage LevelsVOH = f(VOL)VOL = f(VOH)VM = f(VM)EE1418EE14115EE141Mapping between analog and digital signalsMapping between analog and digital signalsVILVIHVinSlope = -1Slope = -1VOLVOHVout“0”VOLVILVIHVOHUndefinedRegion“1”EE14116EE141Definition of Noise MarginsDefinition of Noise MarginsNoise margin highNoise margin lowVIHVILUndefinedRegion"1""0"VOHVOLNMHNMLGate OutputGate InputEE1419EE14117EE141Noise BudgetNoise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sourcesEE14118EE141Key Reliability PropertiesKey Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric –the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;EE14110EE14119EE141Regenerative PropertyRegenerative Propertyv0v1v3finv(v)f(v)v3outv2inRegenerativeNon-Regenerativev2v1f(v)finv(v)v3outv0inEE14120EE141Regenerative PropertyRegenerative PropertyA chain of invertersv0v1v2v3v4v5v62V (Volt)4v0v1v2t (nsec)0⫺11356 8 10Simulated responseEE14111EE14121EE141FanFan--in and Fanin and Fan--outoutNFan-out NFan-in MMEE14122EE141The Ideal GateThe Ideal GateRi = ∞Ro = 0Fanout = ∞NMH= NML= VDD/2g = ∞VinVoutEE14112EE14123EE141An OldAn Old--time Invertertime InverterNMHVin(V)Vout(V)NMLVM0.01.02.03.04.05.01.0 2.0 3.0 4.0 5.0EE14124EE141Delay DefinitionsDelay DefinitionsVouttftpHLtpLHtrtVint90%10%50%50%EE14113EE14125EE141Ring OscillatorRing Oscillatorv0v1v5v1v2v0v3v4v5T = 2 ×tp×NEE14126EE141A FirstA First--Order RC NetworkOrder RC NetworkvoutvinCRtp= ln (2) τ = 0.69 RCImportant model – matches delay of inverterEE14114EE14127EE141Power DissipationPower DissipationInstantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)Peak power: Ppeak= VsupplyipeakAverage power: ()∫∫++==TttTttsupplysupplyavedttiTVdttpTP )(1EE14128EE141Energy and EnergyEnergy and Energy--DelayDelayPower-Delay Product (PDP) =E = Energy per operation = Pav×tpEnergy-Delay Product (EDP) =quality metric of gate = E ×tpEE14115EE14129EE141A FirstA First--Order RC NetworkOrder RC NetworkE01→Pt()dt0T∫Vddisupplyt()dt0T∫VddCLdVout0Vdd∫CLVdd•2== = =EcapPcapt()dt0T∫Voutica pt()dt0T∫CLVoutdVout0Vdd∫12-- -CLVdd•2== = =voutvinCLREE14130EE141Next LectureNext Lecture A First Glance at an
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