EE1411EE1411EECS141EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuitsLecture 26Lecture 26I/OI/OEE1412EECS141AnnouncementsAnnouncements Homework 9 due on ThursdayEE1412EE1413EECS141Class MaterialClass Material Last lecture Timing Clock distribution Today’s lecture I/O Power distribution Intro to adders Reading Chapter 11EE1414EECS141I/O DesignI/O DesignEE1413EE1415EECS141Pads + ESD ProtectionPads + ESD ProtectionDiodePADVDDRD1D2XCEE1416EECS141Chip PackagingChip PackagingChipLL´Bonding wireMountingcavityLeadframePin•Bond wires (~25μm) are used to connect the package to the chip• Pads are arranged in a frame around the chip• Pads are relatively large (~100μm in 0.25μm technology),with large pitch (100μm)•Many chips areas are ‘pad limited’EE1414EE1417EECS141Pad FramePad FrameLayout Die PhotoEE1418EECS141Chip PackagingChip Packaging An alternative is ‘flip-chip’: Pads are distributed around the chip The soldering balls are placed on pads The chip is ‘flipped’ onto the package Can have many more padsEE1415EE1419EECS141Power Power DistributionDistributionEE14110EECS141Impact of ResistanceImpact of Resistance We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution: IR drop Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gatesEE1416EE14111EECS141RI Introduced NoiseRI Introduced NoiseM1XIR⬘R⌬Vpre⌬VVDDVDD⫺⌬V⬘IEE14112EECS141Resistance and the Power Resistance and the Power Distribution ProblemDistribution ProblemSource: Cadence••Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction••Heavily influenced by packaging technologyHeavily influenced by packaging technologyBeforeBeforeAfterAfterEE1417EE14113EECS141Power DistributionPower Distribution Low-level distribution is in Metal 1 Power has to be ‘strapped’ in higher layers of metal. The spacing is set by IR drop, electromigration, inductive effects Always use multiple contacts on strapsEE14114EECS141Power and Ground DistributionPower and Ground DistributionGNDVDDLogicGNDVDDLogicGNDVDD(a) Finger-shaped network (b) Network with multiple supply pinsEE1418EE14115EECS1413 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)3rd “coarse and thick” metal layer added to thetechnology for EV4 designPower supplied from two sides of the die via 3rd metal layer2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routingMetal 3Metal 2Metal 1Courtesy CompaqEE14116EECS1414 Metal Layers Approach (EV5)4 Metal Layers Approach (EV5)4th “coarse and thick” metal layer added to thetechnology for EV5 designPower supplied from four sides of the dieGrid strapping done all in coarse metal90% of 3rd and 4th metals used for power/clock routingMetal 3Metal 2Metal 1Metal 4Courtesy CompaqEE1419EE14117EECS1412 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/VssSignificantly lowers resistance of gridLowers on-chip inductance6 Metal Layer Approach 6 Metal Layer Approach ––EV6EV6Metal 4Metal 2Metal 1RP2/VddRP1/VssMetal 3Courtesy CompaqEE14118EECS141SUPPLYBoardwiringBondingwireDecouplingcapacitorCHIPCd⫹⫺Decoupling CapacitorsDecoupling Capacitors On the board (right under the supply pins) On the chip (under the supply straps, near large buffers)Decoupling capacitors are added:EE14110EE14119EECS141Decoupling CapacitorsDecoupling Capacitors Under the dieEE14120EECS141AddersAddersEE14111EE14121EECS141An Intel MicroprocessorAn Intel Microprocessor9-1 Mux9-1 Mux5-1 Mux2-1 Muxck1CARRYGENSUMGEN+ LU1000umbs0s1g64sumsumbLU : LogicalUnitSUMSELato Cachenode1REGItanium has 6 64-bit integer execution units like this oneEE14122EECS141BitBit--Sliced DesignSliced DesignBit 3Bit 2Bit 1Bit 0RegisterAdderShifterMultiplexerControlData-InData-OutTile identical processing elementsEE14112EE14123EECS141BitBit--Sliced Sliced DatapathDatapathAdder stage 1WiringAdder stage 2WiringAdder stage 3Bit slice 0Bit slice 2Bit slice 1Bit slice 63Sum SelectShifterMultiplexersLoopback BusFrom register files / Cache / BypassTo register files / CacheLoopback BusLoopback BusEE14124EECS141Itanium Integer Itanium Integer DatapathDatapathFetzer, Orton, ISSCC’02EE14113EE14125EECS141FullFull--AdderAdderABCoutSumCinFulladderEE14126EECS141The Binary AdderThe Binary AdderSABCi⊕⊕=A=BCiABCiABCiABCi+++CoAB BCiACi++=ABCoutSumCinFulladderEE14114EE14127EECS141Express Sum and Carry as a function of P, G, DExpress Sum and Carry as a function of P, G, DDefine 3 new variable which ONLY depend on A, BGenerate (G) = ABPropagate (P) = A ⊕BDelete = ABCan also derive expressions for Sand Cobased on D and PPropagate (P) = A +BNote that we will be sometimes using an alternate definition forEE14128EECS141The RippleThe Ripple--Carry AdderCarry AdderWorst case delay linear with the number of bitsGoal: Make the fastest possible carry path circuitFA FA FA FAA0B0S0A1B1S1A2B2S2A3B3S3Ci,0Co,0(= Ci,1)Co,1Co,2Co,3td= O(N)tadder= (N-1)tcarry+ tsumEE14115EE14129EECS141Complementary Static CMOS Full AdderComplementary Static CMOS Full Adder28 TransistorsABBACiCiAXVDDVDDA BCiBABVDDABCiCiABA CiBCoVDDSEE14130EECS141Inversion PropertyInversion PropertyABSCoCiFAABSCoCiFAEE14116EE14131EECS141Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting StagesExploit Inversion PropertyA3FA FA FAEven cell Odd cellFAA0B0S0A1B1S1A2B2S2B3S3Ci,0Co,0Co,1Co,3Co,2EE14132EECS141A Better Structure: The Mirror AdderA Better Structure: The Mirror AdderVDDCiABBABAABKillGenerate"1"-Propagate"0"-PropagateVDDCiABCiCiBACiABBAVDDSCo24 transistorsEE14117EE14133EECS141The Mirror AdderThe Mirror Adder•The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry-generation circuitry.•When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.•The capacitance at node Cois composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .•The transistors connected to Ciare placed closest to the output.•Only the transistors in the carry stage have to be optimized
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