1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on February 13, 2003 by Dejan Markovic ([email protected]) Prof. Jan Rabaey EECS 141 Spring 2003 Homework 4 Due Thu, Feb 20, 5pm @ 558 Cory Problem 1. Propagation Delay Consider a clock network composed of inverters where each stage fans out to more inverters, as shown in Fig. 1. There are a total of three stages: Figure 1: Clock Network At node b1, fan out is 3 inverters At node b2, fan out is 6 inverters At node b3, fan out is 9 inverters At node b4, fan out is 12 inverters There is a load capacitor at the output of every inverter in the final stage. Given that the input capacitance of a minimum sized inverters is Cin, the output capacitor CL is defined as 96 Cin. Assume that Vin will be driven by a perfect step voltage.2 a) First, we have to derive the important technology parameters that are essential in our propagation delay analysis. In the text, we derived the following expression for the delay: )1(intγfttttpoploadrinsicpp+=+= We will determine the parameters of this equation through measurements on two test circuits. For the circuit of Fig.2a, we obtain that tp1 = 5 ns. The delay of a chain of two inverters, Fig. 2b, where the first is minimum sized and the second one is 3 times minimum, equals tp2 = 7ns. Using this information, calculate tpo and γ. tp=5ns1(a)1tp=7ns13(b) Figure 2: Extracting delay parameters tp0 and γ b) Given that the first stage is minimum sized, size the inverters at the remaining two stages such that the propagation delay between Vin and Vout is minimized. c) Using the values you calculated in part (a), and if the inverters are sized as described in part (b), what would be the propagation delay of the first stage? The second stage? The third stage? The total delay? Problem 2. Adiabatic Capacitor Charging Adiabatic charging is a method used to reduce energy dissipation in a system. Typically, this technique is used to reduce dissipation when charging high capacitance loads or loads that require high voltages. We will calculate the energy dissipation of a simple RC circuit given three different types of charging sources as shown on the next page. Figure 3: Simple RC circuit The energy dissipation in an RC circuit is dissipated by the resistor. There are a two ways to calculate the energy dissipation. The first is to calculate the energy drawn by the voltage supply and subtracting the energy delivered to the capacitor. The remaining energy would be the energy dissipated by the resistor. RCVsI s I CRCVsI s I C3 The energy being drawn from the voltage supply is: ∫∞=0 )( )( dttsItsVsE The energy delivered to the capacitor is: ∫∞=0 )( )( dttcItcVcE Alternatively, the energy dissipated can be calculated directly from the R by using the equation: ∫∞=0 )(2 dtRtsIdissE a) Single Step Input b) Ramp Input c) Multi Step Input a) Calculate the energy dissipation of one complete cycle of charging and discharging by a single-step input. Assume that there is sufficient time for the capacitor to fully charge before the start of the discharging. b) Calculate the total energy dissipation for a ramp input. Assume that it takes take time T for the power supply to rise to Vs, and another time T for the power supply to decrease to zero. Also assume that RC << T. As time T is increased, what happens to your energy dissipation?4 c) Calculate the energy dissipation for an N step input. Again, assume that there is sufficient time for the capacitor to fully charge or discharge between each step, and that the steps are evenly distributed between 0 and VS. d) What happens to the energy dissipation as N approaches infinity? Why is that? Problem 3. Sizing and Power CLVoutVin Figure 4: Inverter Chain R = 50 kΩ, Cin = 10 fF, Cintrinsic = 5 fF. In this problem, we will study how sizing affects power consumption. Assume that we have a chain of 5 inverters and that we want to drive a capacitive load. The capacitive load is CL = 3.125 pF. Assume that the above stated resistance and capacitances are for minimum-sized inverters. Our goal is to minimize power consumption and keep delay ≤ 30 ns. Power consumption is typically proportional to capacitance and voltage supply squared. For this particular problem, we will define power consumption as: 2sup ptottotVCP = Assume that capacitance increases linearly with the size when calculating the total capacitance. Decreasing the voltage supply on a circuit will increase the propagation delay by some factor. For our problem, we will simplify this and assume that propagation delay is inversely proportional to the supply voltage. Since we use VDD as the baseline voltage, the delay will be: pVDDSUPPDDpVSUPPtVVt )(= where tpVDD is the propagation delay at VDD and tpVSUPP is the propagation delay at the alternative voltage. There are three different supply voltages that we can use: VDD, VDD/2, and VDD/3, where VDD = 2.5V. The question is, which supply voltage and sizing combination will result in the least power consumption, yet still have a delay that falls within the constraint (≤ 30ns)? To figure this out, find optimal sizing for all three supply voltages and calculate corresponding power consumption. Assume that sizes are increasing in geometric fashion (1, x, x2, x3, x4). This means that the effective fanout of the first four stages is x, while the effective fanout of the last stage is CL/x4. (Such approximation closely approximates variable taper result for optimal stage size.)5 Problem 4. Delay and Energy Capacitance In this problem we have to determine linear equivalent of the inverter input capacitance using HSPICE. Simulation setup is shown in Fig. 5. The transistor sizes in microns are marked on schematics. All transistors are minimum length, L=0.25µm. Dotted inverter at the output is used to suppress excessive Miller kick-back effect on the input capacitance of the previous stage. tccttlinVin2/1 2/1 2/1 8/42/1 2/1CDSuppressesMillerkick-backEcctElinVin2/12/12/1 8/42/12/1CESuppressesMillerkick-back(a) (b) Figure 5: Equivalent delay and energy capacitances a) Determine capacitance CD from Fig. 5a in such a way as to match propagation delays of the inverter loaded with another inverter, delay tcct = (tLHcct + tHLcct)/2, and inverter loaded with equivalent linear capacitance, delay tlin =
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